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I get this warning after synthesis is completed in Vivado. I have a single port ram which is constructed using block memory generator. Its output is connected to Brightness_Contrast module's data_in input but apperantly something is not right. But everything seems right interestingly. How can I solve this issue?? Here is the warning

signal data_out_ram : std_logic_vector(11 downto 0); --in top_module

[Synth 8-3331] design Brightness_Contrast has unconnected port data_in[11]

Here what I have

component Brightness_Contrast
port (
clk_in : in  std_logic;
operation : in std_logic_vector(1 downto 0);
data_in: in std_logic_vector(11 downto 0);
output_of_operation: out std_logic_vector(11 downto 0);
mode: in std_logic
);

component Block_Ram
port(addra :in std_logic_vector(15 downto 0);
     clka : in std_logic;
     dina : in std_logic_vector(11 downto 0);
     douta: out std_logic_vector(11 downto 0);
     wea: in std_logic);
     end component;

U4: Block_Ram port map(addra => address_ram,
                       clka => clk,
                       dina => data_in_ram,
                       douta => data_out_ram,
                       wea => write_enable);

U5: Brightness_Contrast port map(clk_in => clk,
                                 operation => operation,                                
                                 data_in => data_out_ram,
                                 output_of_operation => output_of_operation,
                                 mode => mode);

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity Brightness_Contrast is
generic (
PICTURE_WIDTH_HEIGHT : integer := 250;
COLOR_BIT : integer := 4);
port (
clk_in : in  std_logic := '0';
operation : in std_logic_vector(1 downto 0);
data_in: in std_logic_vector(11 downto 0);
output_of_operation: out std_logic_vector(11 downto 0);
mode: in std_logic
);
end Brightness_Contrast;

architecture Behavioral of Brightness_Contrast is

signal check : std_logic_vector(11 downto 0) := data_in;

begin

       BRIGHTNESS_CONTRAST: process(clk_in,operation,mode) is

       begin

       if rising_edge(clk_in) then --clk

              if operation = "00" then              

              if mode = '0' then 

              if check(3*COLOR_BIT-1 downto 2*COLOR_BIT) < "1110" then
              check(3*COLOR_BIT-1 downto 2*COLOR_BIT) <= ((check(3*COLOR_BIT- 
 1 downto 2*COLOR_BIT)) + "0010");
              end if;

              if check(2*COLOR_BIT-1 downto COLOR_BIT) < "1110" then
              check(2*COLOR_BIT-1 downto COLOR_BIT) <= ((check(2*COLOR_BIT-1 
 downto COLOR_BIT)) + "0010");
              end if;

              if check(COLOR_BIT-1 downto 0) < "1110" then
              check(COLOR_BIT-1 downto 0) <= ((check(COLOR_BIT-1 downto 0)) + 
 "0010");
              end if;

              output_of_operation <= check;

              elsif mode = '1' then 

              if  check(3*COLOR_BIT-1 downto 2*COLOR_BIT) > "0001" then
              check(3*COLOR_BIT-1 downto 2*COLOR_BIT) <= ((check(3*COLOR_BIT- 
 1 downto 2*COLOR_BIT)) - "0010");
              end if;

              if  check(2*COLOR_BIT-1 downto COLOR_BIT) > "0001" then
             check(2*COLOR_BIT-1 downto COLOR_BIT) <= ((check(2*COLOR_BIT-1 
 downto COLOR_BIT)) - "0010");
              end if;

              if check(COLOR_BIT-1 downto 0) > "0001" then
              check(COLOR_BIT-1 downto 0) <= ((check(COLOR_BIT-1 downto 0)) - 
 "0010");
              end if;   

              output_of_operation <= check;

              end if; 

              elsif operation = "01" then   

              if mode = '0' then  

              if   check(3*COLOR_BIT-1 downto 2*COLOR_BIT) < "1000" and  
 check(3*COLOR_BIT-1 downto 2*COLOR_BIT) > "0001" then

              check(3*COLOR_BIT-1 downto 2*COLOR_BIT) <=  
 ((check(3*COLOR_BIT-1 downto 2*COLOR_BIT)) - "0010"); 

              elsif  check(3*COLOR_BIT-1 downto 2*COLOR_BIT) > "0111" and 
 check(3*COLOR_BIT-1 downto 2*COLOR_BIT) < "1110" then

              check(3*COLOR_BIT-1 downto 2*COLOR_BIT) <=  
 ((check(3*COLOR_BIT-1 downto 2*COLOR_BIT)) + "0010") ;
              end if;

              if   check(2*COLOR_BIT-1 downto COLOR_BIT) < "1000" and  
 check(2*COLOR_BIT-1 downto COLOR_BIT) > "0001" then

              check(2*COLOR_BIT-1 downto COLOR_BIT) <=  ((check(2*COLOR_BIT-1 
 downto COLOR_BIT)) - "0010");

              elsif  check(2*COLOR_BIT-1 downto COLOR_BIT) > "0111" and  
 check(2*COLOR_BIT-1 downto COLOR_BIT) < "1110" then

              check(2*COLOR_BIT-1 downto COLOR_BIT) <=  ((check(2*COLOR_BIT-1 
 downto COLOR_BIT)) + "0010") ;
              end if;

              if   check(COLOR_BIT-1 downto 0) < "1000" and  check(COLOR_BIT- 
 1 downto 0) > "0001" then

              check(COLOR_BIT-1 downto 0) <=  ((check(COLOR_BIT-1 downto 0)) 
 - "0010");

              elsif  check(COLOR_BIT-1 downto 0) > "0111" and  
 check(COLOR_BIT-1 downto 0) < "1110" then

              check(COLOR_BIT-1 downto 0) <=  ((check(COLOR_BIT-1 downto 0)) 
 + "0010") ;
              end if;

              output_of_operation <= check;

              elsif mode = '1' then                    

              if  check(3*COLOR_BIT-1 downto 2*COLOR_BIT) < "1000" and 
 check(3*COLOR_BIT-1 downto 2*COLOR_BIT) > "0010" then

              check(3*COLOR_BIT-1 downto 2*COLOR_BIT) <= ((check(3*COLOR_BIT- 
 1 downto 2*COLOR_BIT)) - "0011");

              elsif check(3*COLOR_BIT-1 downto 2*COLOR_BIT) > "0111" and 
 check(3*COLOR_BIT-1 downto 2*COLOR_BIT) < "1101" then

              check(3*COLOR_BIT-1 downto 2*COLOR_BIT) <= ((check(3*COLOR_BIT- 
 1 downto 2*COLOR_BIT)) +"0011") ;
              end if;

              if  check(2*COLOR_BIT-1 downto COLOR_BIT) < "1000" and 
 check(2*COLOR_BIT-1 downto COLOR_BIT) > "0010" then

              check(2*COLOR_BIT-1 downto COLOR_BIT) <= ((check(2*COLOR_BIT-1 
 downto COLOR_BIT)) - "0011");

              elsif check(2*COLOR_BIT-1 downto COLOR_BIT) > "0111" and 
 check(2*COLOR_BIT-1 downto COLOR_BIT) < "1101" then

              check(2*COLOR_BIT-1 downto COLOR_BIT) <= ((check(2*COLOR_BIT-1 
 downto COLOR_BIT)) +"0011") ;
              end if;

              if  check(COLOR_BIT-1 downto 0) < "1000" and check(COLOR_BIT-1 
 downto 0) > "0010" then

              check(COLOR_BIT-1 downto 0) <= ((check(COLOR_BIT-1 downto 0)) - 
 "0011");

              elsif check(COLOR_BIT-1 downto 0) > "0111" and check(COLOR_BIT- 
 1 downto 0) < "1101" then

              check(COLOR_BIT-1 downto 0) <= ((check(COLOR_BIT-1 downto 0)) + 
 "0011") ;
              end if;

              output_of_operation <= check;

              end if; --mode                      
              end if; --Operation                                                   
              end if; --CLK

              end process BRIGHTNESS_CONTRAST ;


  end Behavioral;
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  • \$\begingroup\$ Looks like the answer may lie with the Block_Ram macro - almost like you set it up as an 11 bit output instead of 12 bits. \$\endgroup\$
    – W5VO
    Commented May 6, 2018 at 19:11
  • \$\begingroup\$ No it is true. Actually I get 24 warnings. I just shared one of them. 12 out of 12 bits are not connected, not just one of them. \$\endgroup\$ Commented May 6, 2018 at 19:21
  • \$\begingroup\$ I opened schematics and see that it is connected. \$\endgroup\$ Commented May 6, 2018 at 19:28
  • \$\begingroup\$ But I do not understand why I get this error \$\endgroup\$ Commented May 6, 2018 at 19:28
  • \$\begingroup\$ Did it work in simulation? If not, there may be a logic error somewhere that means the RAM output does not affect any observable signal outputs. This would allow synthesis to trim away any affected parts of the design to save resources. \$\endgroup\$
    – user16324
    Commented May 6, 2018 at 19:45

1 Answer 1

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I do not have a direct answer to your question as it's not obvious to me what you have declared where and what is in which file. But I can give you a few tips how to test and debug such a design.

  1. Simulation is a powerful little helper to verify a VHDL design. As you're quite limited with debug outputs a proper simulation can show you quite easy where things go wrong. A tool I'm always using (like it because it's platform independent) is GHDL in combination with GTKWave.

  2. If a synthesis does run through read all the warnings and errors carefully (actually this is good practise even if the synthesis is succesfull). In case of an error like yours I tend to start reducing my design down to simple parts and verify their functions 1 by 1 until the design breaks again. As your fault is about port mapping, remove all your code and start with just the port mapping.

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