I have been trying to implement a current limiting circuit using a high power NMOS and high side gate driver.
My idea is to adjust the PWM duty-cycle of the gate driver to give an limited (average) current to the load. So far, I had good luck with a small load (8 Ohm at 24V). However, when I try a bigger load (2 Ohm at 24V), the gate driver stops working.
My original guess is that the NMOS gate is taking too much current form the gate driver output pin, but the simulations tell me that the TG pin is only outputting 2.4A max (LTC4440 can do 4A max for 1us). Another guess is that the inductance in the wire make the peak current higher than what the simulations show. Does anyone have a recommendation ?
The schematic below shows my setup. The plot shows the output voltage in green, and the current at at the gate of the NMOS in blue.
Here is more information about the experiment I conducted: The circuit (shown in the schematic) seemed to work great when using a 8 Ohm resistor as a load (at 24V). I was controlling the PWM duty-cycle with a potentiometer, and I was able to vary the (average) load current from 0 to 4A. Then, I changed the load for a 2 Ohm resistor (2000W), which should theoretically draw 12A everytime the FET is on. JHowever, as soon as I started adjusting the duty-cycle of the PWM, the gate driver stopped driving the gate. I went back to the smaller load (8 Ohm), but the gate driver does not drive the gate anymore. The chip seems to have an issue. I had this issue happened to me three times (gate driver fails at higher load, but works well at small loads).