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schematic

simulate this circuit – Schematic created using CircuitLab

Consider this diagram which represents a positive edge triggered D Flip-Flop. In the analysis of this circuit, my book (Morris Mano) says that when the value of D = 0 and Clk is set to 1 then the value of the Reset variable and Set variable are 0 and 1 respectively.

How can it make such a prediction? Clearly, output of NAND4 has to be 1 and lower two inputs of NAND3 have to be 1 but the above input can be either 0 or 1. Also, one input each of NAND 1 and 2 has to be 1. But their outputs can be 0, 1 or 1, 0 respectively. Hence the value of S can be 0 and that of R can be 1. Then why is everyone so sure that R has to be 0 making the output Latch always in a Reset state. May someone help?

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  • \$\begingroup\$ Truth tables are Always and data sheets you should take a look 4013 is the CMOS D flip-flop \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 May 8 '18 at 0:00
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    \$\begingroup\$ I’m sorry, what? \$\endgroup\$ – Matt May 8 '18 at 3:21
  • \$\begingroup\$ Sorry that was a Siri translation error and should read on data sheets. Search for 74HC74 And look at the truth table. Also it is not implemented the way you suggest but rather uses transmission gates or switches with CMOS . The output Q is a result of the rising edge of clock sampling the D input. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 May 8 '18 at 16:10
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You have to consider that CLK is a toggling signal. If we want to analyze what happens when CLK = 1, we have to consider first what happened before the rising edge of CLK, when CLK was 0.

When CLK was zero the inputs of the upper Set-Reset FF formed by NAND1 and NAND2 where Set=1, Reset=0. Now, when the inputs of that FF pass from 1-0 to 1-1 their outputs are uniquely defined, with S (its negated output) being 1. From this point I guess you can finish the analysis alone.

As a conclusion of your analysis you will also understand why it is important for D to be stable while CLK is toggling.

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  • \$\begingroup\$ Okay, I think I got most of your answer. Can you please elaborate the truth table for case when Clk is 0? \$\endgroup\$ – Matt May 9 '18 at 8:27
  • \$\begingroup\$ What if CLK=1 and D=1 (beforehands, s was 1 and r was 0) ? I wrote it down and the new s and r came out as s=1 r=0 which is reset state. Hut the book says it is undefined state. Why?! \$\endgroup\$ – parvin May 13 at 13:33

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