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On the product I am designing, I have an input connector of 60 lines and an output connector of 32 lines.

The input can be connected to different outside products and then the lines can be mixed, so the idea of the product is, more or less, to remap the relevant input lines to the output ones.

For example, the output line Number1 can be connected to the input line number 1 or the number 2 or 55. Same thing for number 2. Meaning my product is more or less a huge multiplexer between 60 inputs and 32 outputs.

The first that came into my mind to do that fairly easily, and to be able to change the configuration if needed in the future, is using a CPLD. My problem is that I am inexperienced with CPLD and I do not know at all at what kind of characteristic I should look for in the datasheet.

Would this kind of project take a lot of resources in a CPLD?

What are the characteristics that I should look for to be sure the CPLD I choose will have enough resource (flip-flop? gate? macrocell?)?

How can I do a rough estimation of the required resources for this kind of project?

Edit

To add information there is actually two different possibilities for the CPLD that arised from previous answers. First possibility is to just do what is required statically, meaning once the CPLD is programmed the configuration between input and output will not change until the next programmation.

The second possibility is to be able to change the configuration dynamically without reprogramming the CPLD, for example by SPI would be nice.

The questions I asked before are for both possibilities.

Also My inputs are synchronized between each other and the maximum frequency will probably be around 5MHz, how do I estimate the delay between input and output and the desynchronization due to the different paths in the CPLD?

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  • \$\begingroup\$ What timing constraints do you have? The signal will take a (short) amount of time to traverse a CPLD. I assume the rest of the question is about statically routing up to 32 of 60 inputs to up to 32 outputs. \$\endgroup\$ – Peter Smith May 8 '18 at 13:04
  • \$\begingroup\$ Would the usage of the lines in a given installation be fixed or could attached items be changed by the user? \$\endgroup\$ – Peter Smith May 8 '18 at 13:15
  • \$\begingroup\$ @PeterSmith, I unfortunately do not have all the specification, but I think the fastest signal passing through the CPLD would be at 5MHz. meaning I need propagating dela to be less than that I think. What woul be a typical propagation delay for this kind of project? \$\endgroup\$ – damien May 8 '18 at 13:16
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If all you're doing is routing any 32 of 60 inputs to 32 outputs, then the cell requirements are simple: Qn = Dn. I don't see need for flip flops, just a non-inverting gate between output and input. Your i/o and pin count must be considered: 92 i/o and corresponding pins. You could use a single device, such as a 144 pin TQFP (Altera 5M240Z) or split into two smaller devices, such as the 64 pin 5M40Z. Look at power dissipation and speed when making your selection to assure it meets your system requirements. You might also need level translators to make i/o compatible with the CPLD.

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    \$\begingroup\$ If the assignment is dynamic (determine what is connected at startup and then assign routes), it becomes a little bit more complicated. \$\endgroup\$ – Peter Smith May 8 '18 at 13:08
  • \$\begingroup\$ @AlmostDone, Ok so if I understand well, reptty much any CPLD would do? \$\endgroup\$ – damien May 8 '18 at 13:11
  • \$\begingroup\$ @PeterSmith Agree, if that is in fact the case. I inferred from OP's statement: "be able to change the configuration if needed in the future" that configuration would be static over the course of multiple instances of the product, but with the ability to change for different versions. This could be via JTAG port at time of manufacture. \$\endgroup\$ – AlmostDone May 8 '18 at 13:12
  • \$\begingroup\$ @Peter Smith, it is not supposed to be dynamic but a feature I though of would be for example to have a microcontroller next to it and by a serial communication between the microcontroller and CPLD to change the mapping. Like for example the user could say to the microcontroller through USB iterface, I want this input connected to this output, and the microcontroller would change that in the CPLD, would it be possible? \$\endgroup\$ – damien May 8 '18 at 13:14
  • \$\begingroup\$ @damien Unless there are other requirements you haven't mentioned, I believe so. \$\endgroup\$ – AlmostDone May 8 '18 at 13:14
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A CPLD is a reasonable-enough choice. A typical CPLD on the market today will be a pile of logic blocks (different vendors use different terms), each consisting of a 4-input LUT and a register (flip-flop). Both the LUT and the register can be configured and can be used together or independently.

You can read plenty about the function of a LUT and of a configurable register on plenty of websites. Suffice to say that the LUT is a little logic gate circuit with 4 logic inputs and 1 output. The LUT output bit values for each of the 16 possible 4-bit input values is specified during configuration. So the LUT can impersonate any logic gate circuit with 4 inputs and 1 output. Including a small mux.

There's carry logic with the LUT in some CPLDs than can be exploited to make a larger mux but let's keep this simple and say that 1 LUT can use 3 inputs to make a 2-to-1 mux with a single select line.

You want 32 x 60-to-1 multiplexers ('mux'es) plus some interface logic to let you select the path through each mux. So you use muxes into muxes into muxes to make a 60-to-1 mux out of lots of 2-to-1 muxes. Specifically, you can use 30 + 15 + 8 + 4 + 2 + 1 mux = 60 muxes. The first 30 muxes take 60 inputs and produce 30 outputs, the next 15 muxes take 30 inputs and produce 15 outputs and so on, through six mux levels to produce a 1 bit result.

You want 32 of these so that's 32 x 60 muxes = 1920 muxes = 1920 LUTs. You then want logic to select the path, which is one register per LUT. The register will be configured to be a D-type Flip-Flop (DFF). Register and LUT come as a pair so that's convenient because your 1920 LUT CPLD will automatically come with the 1920 registers needed to control the 1920 LUTs.

You then need some sort of interface to accept control information for the routing selection on each mux. SPI, parallel bus, an enormous row of switches, summat else - that's up to you to decide. That requires some logic too and depends on your choice.

Finally, you need enough pins to carry your 60 inputs, 32 outputs, control interface, logic clock and reset. Your CPLD might have an internal oscillator, might be able to produce an internal reset. The oscillator frequency should be as low as possible to get the job done, to reduce unnecessary EMI emissions from it.

So look at CPLDs with at least 2100 LUT/register pairs and enough pins for the interface and 94 more and you'll be on the right path. At that point, cost, capacities for a part family and availability of parts steer you the rest of the way.

As alluded to earlier, some CPLDs can use carry logic to make a 4-to-2 mux with 1 select line so that would use something like half the LUTs of this example. If it were me, I'd design the circuit in VHDL and synthesise it into different guess-start CPLDs using the manufacturer's free software. Then I could see what a particular CPLD family can do with my circuit and to guide my selection. Don't use more of 70..80 % of the device's capacity, to allow for future expansion - pick a larger device instead.

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  • \$\begingroup\$ Thank you very much for this very detailed answer, I am just a bit confused between your answer and the one AlmostDone gave me. because yours seems to use a lot more ressource than what AlmostDone suggested? is it because in your answer you take into account that I can re program he MUX through SPi or something like this? \$\endgroup\$ – damien May 8 '18 at 13:54
  • \$\begingroup\$ @Damien, do you need to be able dynamically reconfigure your arrangement i.e. send data to the CPLD to change the settings but not have to reprogramme it? Please can you edit and improve your question to make that clear. (Please don't add detail in comments, otherwise readers have to piece it all together.) Thanks. \$\endgroup\$ – TonyM May 8 '18 at 14:32
  • \$\begingroup\$ I have edited the question to be clearer does that help? \$\endgroup\$ – damien May 8 '18 at 14:46

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