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I'm sorry if the phrasing is somewhat weird, but the question is hard to articulate. I've created an IC Sample-and-Hold where I have a hold capacitor at the output. I want to charge this capacitor while the clock is high, but also after the signal has stabilized. Is there anyway to delay the clock signal for around 0.2xPeriod (to make it sample after stabilization), and make it fall off again after around 0.4xPeriod (before the clock turns off).

Attached is a figure of what I'm looking for. Above is the clock signal supplied to the circuit, below is the ideal sample signal I want to derive from the clock signal.

enter image description here

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  • \$\begingroup\$ There's a lot of ways to implement this – all of them are specifically useful for a some set of conditions. So, is your time scale correct, i.e. are we talking about a clock in the MHz range, with an amplitude of 1.25 V? What's the drive strength? \$\endgroup\$ – Marcus Müller May 8 '18 at 15:55
  • \$\begingroup\$ Correct timescale. Main clock is 1MHz, with an amplitude of 1.2V. The sample signal has to be able to drive a load of no more than a few fF, all parasitic capacitances. I'm looking for a simple circuit, with as few transistors as possible, as this will simplify the layout. \$\endgroup\$ – Henrik Klev May 8 '18 at 16:01
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    \$\begingroup\$ Is your question targeted to IC design (eg. CMOS)? It is not obvious from your question, but may be the case since you stated you created an IC S&H circuit. \$\endgroup\$ – Sven B May 9 '18 at 9:19
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The analog way

The straightforward way is the following:

  1. Convert square wave to harmonic (sinusoidal)
  2. Delay that with a filter
  3. use a comparator with a fixed threshold to achieve your fixed duty cycle

Luckily, step 1 is usually nothing but a low-pass filter (i.e. an RC filter), so by adjusting that, you can implement step 2 just on the way.

The comparator can actually be a comparator IC / circuit, or just a single appropriately biased transistor.

Advantages

  • cheap
  • works with much higher frequencies, too

Disadvantages

  • relies on analog component tolerances
  • might hence be intense to tune

The full PLL way

  1. Get a VCO at a nominal frequency N·1 MHz, e.g. N=16
  2. Get a PLL IC, or build a PLL circuit, with a clock factor of N
  3. Discipline your PLL using your 1 MHz clock
  4. use simple binary counters, reset by the input clock, on the VCO-generated clock to implement your delay and your duty cycle appropriately

Advantages

  • Street cred
  • much lower jitter and much higher accuracy than RC-filter-based approach
  • high flexibility

Disadvantages

  • needs PLL, VCO
  • design effort might be higher

The lazy digital way

  1. Define an acceptable jitter for output vs 1 MHz input
  2. Get a CPLD or FPGA with an integrated or external clock source >> 1 MHz; the amount by which that clock needs to be higher than 1 MHz depends on the acceptable jitter.
  3. Implement a counter for high-speed clock cycles happening while your 1 MHz clock does one -> period estimate
  4. implement your delay and duty cycle digitally

Advantages

  • Low component count
  • small CPLDs and FPGAs are cheap
  • Digital only: small dependence on environmental specs
  • high flexibility (you can adjust your 1 MHz as much as you like, as long as the CPLD/FPGA can divide the number of clock cycles just like you want it to, everything is frequency-adaptive)

Disadvantages

  • Design complexity
  • quantization of possible delays and duty cycles

The crazy way (a.k.a. Müller proposes a hack)

Your off-on-off sequence can also be implemented by some shift register producing some 0, then some 1, then some 0 again. Let's say you have another clock running at a fixed 10 MHz, and it's good enough.

Just use a shift register (chain) with parallel latchable preload inputs, and a datain/dataout serial interface. Hard-wire the parallel preload inputs to said sequence (which needs no external components, just solder bridges to GND and VCC); hard-wire the datain to ground. You use the rising edge of your 1 MHz signal to latch in the sequence, and use the free running 10 MHz clock to push out the bits to the receiver.

Instead of implementing this using shift register ICs, you can just as well use a microcontroller in SPI slave mode and use the external clock to assert the chip select line (might need further hacking). That would allow for adjustable sequences, and very low integration cost.

What you've then basically built is something like a ROM that contains the signal you want to generate, which you read out sequentially at a higher frequency than your input frequency. You use the input clock to reset the ROM "address" to the beginning of your sequence.

Advantages

  • I propose this hack
  • It's cool
  • Future engineers will be in awe
  • Did I mention it's cool?
  • Low component count and cost

Disadvantages

  • I propose this hack
  • It sounds cool
  • The clocks run asynchronously, so this depends on your higher clock being relatively stable in frequency, when compared to your input clock
  • Might not be trivial to explain
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  • \$\begingroup\$ +1 for street cred. \$\endgroup\$ – remcycles May 22 '18 at 22:18
  • \$\begingroup\$ +1 for discipline your PLL. \$\endgroup\$ – nekomatic May 23 '18 at 9:00
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If you have a triangle wave, or sawtooth wave, then use an analog comparator with adjustable threshold.

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  • \$\begingroup\$ doesn't even need to be triangular or sawtooth – a sine will do just as fine, only that the relation duty cycle/threshold isn't proportional anymore. \$\endgroup\$ – Marcus Müller May 9 '18 at 14:26

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