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I have hooked up the following circuit:

Also, is there any possibility to create a link for the schematic? After posting it I realized it´s too small to be seen but I don´t know how to fix it.

schematic

simulate this circuit – Schematic created using CircuitLab

It´s a simple current source that charges C1 to reach a certain value and saturate OA1 positively to get around 3.7 Volts in its output. Q2 and Q3 form kind of a flip-flop circuit, where the voltage V1 is the output, and it´s set on when V2 is High(3.7 V). Soon after, as a result, V1 will remain on regardless of the state of V2.

Done that, V1 ~ 4.9 V. It will discharge C1 via Q4, and hold Q1´s collector close to 0. But that´s still not the problem.

The problem is:

When V1 ~ 4.9V , it´ll start charging C2, and the same thing should happen(now, set Vout ~ 3.7V), but the voltage across C2 reaches 1.56V and sometimes even 1.57V, though it can´t go over. I tried replacing the op-amp and capacitors but nothing changed. Additionally, when I disconnect V3 from Q6 collector, the circuit works in the expected way( the capacitor reaches 1.56v and latches on the op-amp to positive rail).

So from my first thought what might be causing a problem here is the trial to discharge C2 via Q8. But I don´t know why is that since V1 can easily discharge C1 by the same method.

schematic

simulate this circuit

Am I missing something?

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  • \$\begingroup\$ You might want to limit the schematic you show to just the relevant portion of it. If you want to include context, possibly put the whole circuit and then a close-up of the relevant part of it? \$\endgroup\$
    – Hearth
    Commented May 9, 2018 at 0:03
  • \$\begingroup\$ Yeah that can be interesting. I think I´ll separate in two schematics. Thank you. \$\endgroup\$ Commented May 9, 2018 at 0:07
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    \$\begingroup\$ the second schematic is different from the first .... R20 and R24 are no longer connected to ground \$\endgroup\$
    – jsotola
    Commented May 9, 2018 at 5:06
  • \$\begingroup\$ @jsotola My bad. Gonna correct it now. R20 and R24 should be grounded. Thank you. \$\endgroup\$ Commented May 10, 2018 at 1:12

1 Answer 1

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Emitter and collector for Q2 in the first block (Q6 in the second), Q4 in mine are inverted. Try to put higher potential points upper.

Also the discharge transistor seems to be open before the latch triggers making a negative feedback that keeps C voltage at the ref voltage. Added a resistor from the base to emitter that keeps the transistor closed until the latch triggers.

Also, please, use OA with power rails otherwise the output voltage can go up to kV orders when used as comparator.

With that tweaks the schematic and works as intended.

schematic

simulate this circuit – Schematic created using CircuitLab

The quality of the simulation software also doesn't help to much.

Update, the pull down resistor must be even lower to be less than 10k || 2k2, maybe 1k as the latch to trigger before opening T8 and a capacitor to delay Q2 opening a bit

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  • \$\begingroup\$ Thank you for your answer Dorian. The Latch circuit was wrongly drawed here but in practice i´ve assembled it correctly, exactly the you showed in your post. Tried adding that pull-down resistor but still it didn´t work \$\endgroup\$ Commented May 11, 2018 at 23:44
  • \$\begingroup\$ @IronMaiden , I see the error, the OA output resistor (R8 in my schematic) is parallel to R9 before trigger. Put a lower R14 resistor. 1k maybe. I cannot simulate the circuit now. \$\endgroup\$
    – Dorian
    Commented May 12, 2018 at 7:24

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