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For my master's thesis in computer science, I need to read out a TCD1304AP linear CCD sensor. A STM32 microcontroller with the circuit laid out on a breadboard gets the job done, but in order to make my project more portable, I designed and ordered a PCB from elecrow. Unfortunately, with the manufactured PCB I get a lot of noise on the ADC when reading out the sensor.

Here is the link to the datasheet of the linear CCD sensor, you can find the schematic of the necessary circuit on page 12: link

I have the layout of my PCB attached with some important remarks:

PCB layout

As you can see, the input from the IO pins gets inverted at the Logic Inverter and then goes on to the pins of the TCD1304 sensor. Some pins are clocked at a high rate (e.g. masterclock @ 4MHz). The resistors and transistors are placed like the schematic excepts them, there is also a LT1761 added for voltage regulation. The output reading I get from the ADC looks really noisy, much worse than the output I get from the breadboard circuit.

Hopefully some of you can tell me the major mistakes in this PCB, as I'm pretty much a newbie in electronics and PCB design!

EDIT:

Here is the full schematic:

PCB schematic

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    \$\begingroup\$ Can you post your full schematic as well? \$\endgroup\$ – awjlogan May 9 '18 at 12:23
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    \$\begingroup\$ The first thing that jumps out is you have no decoupling for the logic or CCD. \$\endgroup\$ – Colin May 9 '18 at 12:25
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    \$\begingroup\$ Your VCC line seems to be meandering around quite a lot, and it's very thin for a power trace. \$\endgroup\$ – Hearth May 9 '18 at 12:26
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    \$\begingroup\$ Looks autorouted \$\endgroup\$ – pipe May 9 '18 at 13:50
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    \$\begingroup\$ Decoupling capacitors are not close enough to the pins. \$\endgroup\$ – lucas92 May 9 '18 at 14:06
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Pin assignment is wrong for the 2SA105 transistor:

  • The PCB's square pad, pin 1, is the base on PCB and schematic, when base is pin 3 on the transistor.
  • The PCB's center (and, incorrectly, offset) pad, pin 2, is the emitter on PCB and schematic, when emitter is pin 1 on the transistor.
  • The PCB's other pad, pin 3, is collector on PCB and schematic, when collector is pin 2 (center) on the transistor.
    2SA105 pinout

Therefore, with that PCB, assuming the transistor is mounted on the same side as the 74HC04 (that is, opposite the TCD1304AD), one must

  • offset the center pin of the transistor slightly in the direction opposite to the flat;
  • introduce the transistor with that center pin farthest from the PCB's square hole, and turned so that the other pins fit not too unnaturally;
  • double-check before soldering.

Of course I can't tell how things are on the prototype. But if the transistor was mounted wrong, the emitter-follower buffer at the output of the CCD would not work properly, and (depending on which of the 5 wrong ways the transistor is mounted) that could prevent operation or blur the result horribly.


As noted by others: the existing decoupling capacitors C2 C3 C4 are poorly routed. And the routing of Vcc is unnecessarily long, which contributes to the poor decoupling. That's my distant second hypothesis at the cause of the problem observed.

It is blatantly ignored the golden rule of decoupling capacitors: the loop area, length and (to a lesser degree except for high-power applications) resistance of the loop formed with the IC they decouple must be minimized.

Further, it would be slightly challenging to mount them all on the same side: the 10uF is in cramped space.

With that PCB, one should mount decoupling capacitors directly across what they decouple, especially a 10uF capacitor across pins 1&2 (+) and 22 (-) of the TCD1304AD (on the solder side of that, which is also the component side for at least the 74HC04); and a 0.1uF across pins 7 and 14 of the 74HC04. It is OK (perhaps best) not to remove the existing decoupling capacitors if already soldered.


I would add a capacitor on the unregulated 5V power supply input, perhaps 1uF tantalum. Such capacitor is shown on the application schematic of the regulator, and quoting the LT1761 datasheet:

A bypass capacitor is required on this pin if the device is more than six inches away from the main input filter capacitor. In general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits.

The LT1761-BYP pinout looks OK to me (it is on the side opposite to the view, as the 74HC04 is, and some of the yellow pixels interrupt the green traces). The target Vcc of 4V is reasonable and can be achieved with the +5V at -10% tolerance.


As noted by others: the relative placement of the CCD, buffer transistor, and connector, is not ideal. If mechanical constraints allow, it would be best to put the transistor (and associated resistors) in-between, as in the logical schematic. However we are not talking very high-frequency here, and things are not disastrous.


Pin assignment of the connector differs on schematic and PCB

Ground is pin 5 of PCB, pin 1 on schematic. The PCB pinout is best, because it tends to use ground as a shield of the analog output from the influence of digital signals.

Experience (and amazingly, mostly personal or at least close one) teaches that

  • carefully keeping schematic and PCB in synchronization takes mere minutes, but saves weeks and huge money;
  • having a schematic and PCB design reviewed by others before producing it works; but not nearly as well as after experiencing problems.
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May I present the LT1761 regulator circuit complete with recommended capacitors on inputs and outputs: -

enter image description here

On your PCB design I see only a 10 nF capacitor. I also don't see a device footprint that matches the footprints shown in the data sheet but I could be mistaken about this. Looking at the circuit you have linked....

enter image description here

Try and learn to use vias and be clever about avoiding routing on the ground layer. Think about this for instance: -

enter image description here

The ground flood will be much better just for a bit of thinking about the problem. Make your supply lines (orange) much thicker too AND think about how they route - look how yours pointlessly splits around the 10 nF capacitor!

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    \$\begingroup\$ It's down at lower right. It's not doing much good there, but it is there. \$\endgroup\$ – WhatRoughBeast May 9 '18 at 13:02
  • \$\begingroup\$ @WhatRoughBeast it's all a bit of a mess. \$\endgroup\$ – Andy aka May 9 '18 at 13:08
  • \$\begingroup\$ Your orange additions are a good start, but they miss the most important connection - to Vcc of the CCD. \$\endgroup\$ – WhatRoughBeast May 9 '18 at 13:28
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    \$\begingroup\$ @WhatRoughBeast would you have me relay the whole PCB for him LOL? I think he might be able to see how this may be done with a flood through on the top layer now. \$\endgroup\$ – Andy aka May 9 '18 at 15:00
  • \$\begingroup\$ Well, maybe. He seems totally at sea with the whole decoupling thing, and I'm afraid he might take your modification as prescriptive. \$\endgroup\$ – WhatRoughBeast May 9 '18 at 18:49
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As has been mentioned in comments, your decoupling/power distribution is abominable.

Move your regulator to the top of the board. The closest components to the CCD Vcc should be the decoupling caps (at least the 10 uF shown in Andy aka's figure, and a 0.1 won't hurt either). The power trace should be much wider - 0.1 inch would be a good starting point, and the connection from the decoupling caps to the CCD should be as short as you can make it.

Additionally, another 0.1 uF on the Vcc of the inverter is good practice.

If I were you, I'd also rotate your IO connector 90 degrees, with the digital on the left and the output pin on the right.

For high frequencies, and logic edges definitely count in this context, the worst thing you can do is place the caps far from the point of use. Trace inductance and resistance are the big problems, and the answer to both issues is short and wide.

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Besides of the decoupler capacitor, I would try to find a better route for the ADC signal, it is very close to the 4MHz and 200khz high frequency lines, which could induce some noise in your ADC signal.

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I think your schematic (what I bothered to decode of it) is fine but the decoupling caps are WAY too far from the CCD Vcc pin and meander through the inverter connections.

Stick a couple leaded MLCC 1uF caps on the bottom linking the Vcc and GND of the inverter and the CCD (one each) and see if it works better.

And next time, lay out the caps as close as possible to the supply pins. It's best to lay out the power connections first and then the signal connections.

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I'm puzzled you didn't take the time to look at the pcb-layout in the zip-file where you found the schematic. It may not be perfect, but many of the suggestions you've already received are actually taken into account in this layout.

As fgrieu already noted, the transistor in TO-92 package has a different pin-out than in the schematic (which is for the SOT23-version of the transistor), and you should add a 1uF cap across Vcc and GND before the LDO (this is added to the latest revision (C5 in the image below), which is not yet published, because I only just received the new boards from the factory yesterday): TCD1304 pcb from tcd1304.wordpress.com

Finally I should mention that a lot of the noise that you are seeing stem from the connection between the tcd1304 pcb and the stm32-board. I've been in contact with a person in Schwitzerland who made the TCD1304-pcb as a "shield" for the nucleo-board, and the much reduced wire-length significantly reduced the noise.

ps I hope you'll remember to cite the source of the circuit diagram correctly and/or firmware for the stm32 correctly in your thesis.

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  • \$\begingroup\$ Therefore there are now at least 3 PCBs for a comparable schematic (pinouts of the connector, side of components, used of SMD.. differ), including this one. \$\endgroup\$ – fgrieu May 14 '18 at 11:11

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