I have a function f(x,y,z,w)=x.y.z+ y’.z’+x’.w’ and I need to make a circuit using two 3 to 8 decoders, an inverter, an or gate with as many inputs as we want (I use two because I need a 9 input one and on DEEDS I found up to 8) and up to 16 and gates (???). So far I've made this circuit based on the fact that f= Σ(0,1,2,4,6,8,9,14,15).
Why is this happening? Aren't the outputs of the decoders the minterms of the function? (e.g. D0= x'y'z'w') Also, any suggestion about the AND gates and the solution? No need for the full solution just some help to guide me.