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I am trying to use some of the builtin vivado libraries to generate two clocks. I have never used any of the builtin functions before.

wire clkfb;
wire clk_324p;
wire clk_324n;
wire clk_200p;
wire clk_200n;
MMCME2_BASE#
(
    .CLKFBOUT_MULT_F(52.0),
    .CLKIN1_PERIOD(10.0),

    .CLKOUT1_DIVIDE(16),
    .CLKOUT2_DIVIDE(26)
)
clkgen
(
    .CLKFBIN(clkfb),
    .CLKFBOUT(clkfb),

    .CLKIN1(clk_100),
    .PWRDWN(1'b0),
    .RST(1'b0),

    .CLK_OUT1(clk_200p),
    .CLK_OUT1B(clk_200n),
    .CLK_OUT2(clk_324p),
    .CLK_OUT2B(clk_324n)
);

wire sys_clk_p;
wire sys_clk_n;
wire clk_ref_p;
wire clk_ref_n;

BUFG sys_clkp_buf(.I(clk_324p), .O(sys_clk_p)); 
BUFG sys_clkn_buf(.I(clk_324n), .O(sys_clk_n)); 
BUFG ref_clkp_buf(.I(clk_200p), .O(ref_clk_p)); 
BUFG ref_clkn_buf(.I(clk_200n), .O(ref_clk_n)); 

When I try the run the simulation I get the errors...

ERROR: [VRFC 10-426] cannot find port CLK_OUT2B on this module [/home/chase/workspace/SVESample/src/top.v:53] ERROR: [VRFC 10-426] cannot find port CLK_OUT2 on this module [/home/chase/workspace/SVESample/src/top.v:52] ERROR: [VRFC 10-426] cannot find port CLK_OUT1B on this module [/home/chase/workspace/SVESample/src/top.v:51] ERROR: [VRFC 10-426] cannot find port CLK_OUT1 on this module [/home/chase/workspace/SVESample/src/top.v:50] ERROR: [VRFC 10-2063] Module not found while processing module instance [/wrk/2018.1/nightly/2018_04_04_2188600/data/verilog/src/unisims/MMCME2_BASE.v:111] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/chase/workspace/SVESample/src/top.v:61] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/chase/workspace/SVESample/src/top.v:110] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

It seems like the simulator does not know about the builtin libraries. Do I need to somehow include them in the project or something? I thought I could just straight up use them.

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I tried your code and after some initial problems got different errors. Most noticeable was Module "<MMCME2_ADV> not found while processing module instance <mmcm_adv_1> " which if you open the MMCME2_BASE.v module is inside it.

Then I decided to work very meticulous so I copied the ports from the MMCME2_BASE.v Xilinx source code and connected the module up exactly that way. That made it work.

I compared the code and found that your port names are wrong:
CLK_OUT1 should be CLKOUT1
CLK_OUT1B should be CLKOUT1B
etc.

This works:

   .CLKFBOUT (clkfb), 
   .CLKFBOUTB(),
   .CLKOUT0  (),  
   .CLKOUT0B (), 
   .CLKOUT1  (clk_200p),  
   .CLKOUT1B (clk_200n), 
   .CLKOUT2  (clk_324p),  
   .CLKOUT2B (clk_324n), 
   .CLKOUT3  (),  
   .CLKOUT3B (), 
   .CLKOUT4  (),  
   .CLKOUT5  (),  
   .CLKOUT6  (),  
   .LOCKED   (),   
   .CLKFBIN  (clkfb),  
   .CLKIN1   (clk_100),   
   .PWRDWN   (1'b0),   
   .RST      (1'b0) 
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  • \$\begingroup\$ I need to check. I thought I copied the names from the documentation. Thanks. \$\endgroup\$ – chasep255 May 11 '18 at 12:14
  • \$\begingroup\$ I always go straight to the source because the ports are nicely formatted and even the documentation can be wrong. But beware to set the file or editor to read-only! \$\endgroup\$ – Oldfart May 11 '18 at 12:16
  • \$\begingroup\$ Did you compile the unisims (primitives like BUFG) library? Others are xilinxcorelib for higher level modules that use unisims, and simprims for netlist. In general, you shouldn't need to instantiate BUFG primitives in your RTL, but it isn't wrong. compile them somewhere, usually a separate library, and point to them in your script using include and/or -L... you can also use `include in your code, but better to manage in script usually \$\endgroup\$ – CapnJJ May 11 '18 at 13:53
  • \$\begingroup\$ For some reason you don't have to compile anything or even provide a link to the library or Verilog directory. It "just" works, which I don't like because it is against the way Verilog compilers work. (Also it leaves you in the dark, if for some reason it does NOT work) \$\endgroup\$ – Oldfart May 11 '18 at 15:47

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