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I need to drive a inductive load with a triac dimmer. Circuit uses zero-voltage cross and delay for gate trigger. An additional circuit for detecting zero current cross has been added. So, what are the correct steps in order to safely control power for a highly inductive load? -> zero-volt cross, delay, trigger triac, delay, detect zero-current, trigger triac. enter image description here enter image description here

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  • \$\begingroup\$ Being a inductive load with switch, plus voltage peak protection? \$\endgroup\$ – Jose May 11 '18 at 10:47
  • \$\begingroup\$ the load is a universal ac motor or a transformer, no voltage peak protection, nor inrush current, at the moment. \$\endgroup\$ – johnger May 11 '18 at 10:49
  • \$\begingroup\$ Add some schematics about the gate driving and triac, snubber, etc..compete schematics. \$\endgroup\$ – Marko Buršič May 11 '18 at 12:14
  • \$\begingroup\$ uploaded schematic for dimmer, and zero current detection circuit. \$\endgroup\$ – johnger May 11 '18 at 12:20
  • \$\begingroup\$ for a resistive load, zero-volt cross and delay is enough, as current is synchronized with voltage. but for the inductive loads, would the zero current detection and re-trigger of triac be enough ? or correct ? \$\endgroup\$ – johnger May 11 '18 at 12:23
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You can set a timed interrupt, let's say every 100 microsecond. You fire a short pulse, like set output to 1 then execute few NOP, or maybe a while loop, so that pulse last approx 50 microseconds and then reset the output to 0. Wait interrupt

Then you repeat this until the phase angle almost reaches the end - let's say 20 degrees before half period ends.

From my knowledge there is no other option with this dimmer, since you don't have a feedback of triac state.

TI note:

TI

needs to swap:

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ but i do have the zero-current feedback from triac and the zero-voltage from Line.To my understanding, with inductive loads, current lags and triac must be re-triggered to maintain latching current.From AN307 (ST) "To ensure correct operation, the gate pulse should be synchronized with the triac current zero point and should be long enough to enable the main current to reach the latching current IL level." My doubt is about the correct usage of both zero current and voltage cross. Before trying pulse train option(no need for current sync), i would like to understand Single pulse triggering. \$\endgroup\$ – johnger May 12 '18 at 20:51
  • \$\begingroup\$ Please add a link of circuit description. I don't see a zero-current feedback, only voltage zero-cross with R1 and R2. From AN307 see Fig.3. With voltage zero cross, you can set the phase angle. With inductive load, the current zero cross will be delayed with respect of voltage. If you want a load to be full on, then your driving should be as in Fig.3 Only if you have a current feedback, you can repeat/until train pulses until you detect the triac has latched on. \$\endgroup\$ – Marko Buršič May 13 '18 at 12:01
  • \$\begingroup\$ that would mean using a voltage monitor with a threshold value for correct pulse train. Before that, AN307 mentions "Gate Current Control by Single Pulse" which i am currently trying to achieve. Triac circuit mouser.com/catalog/specsheets/stevalill004v1.pdf and current-zero cross ti.com/lit/an/slaa043a/slaa043a.pdf (pag.16). \$\endgroup\$ – johnger May 13 '18 at 13:05
  • \$\begingroup\$ If you implement current detector, then single pulse is enough, still you have to retrigger if it fails to latch. Much complicated hardware and software. Keep in mind that you would need to swap the TI's ZCD circuit, since the PSU is connected upside down compared to classic way like ST app note. \$\endgroup\$ – Marko Buršič May 13 '18 at 13:30
  • \$\begingroup\$ i did connected the ti's zcd to the inverted supply accordingly st's circuit. still have to finish firmware, will check with oscilloscope when or how fail to latch occurs, varying the pulse width or using single pwm burst if my supply is too weak for single pulse. \$\endgroup\$ – johnger May 13 '18 at 13:54

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