which is the best possible way to perform Schematic vs Schematic for 2 Verilog gate-level codes?
I want to do Svs just like people do for LvL in case of layout vs layout. SvS is also available for spice netlist.
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I think you are referring to what is called formal equivalence checking. When you make changes to a gate-level net-list to meet timing, loading, or any other optimization goals, an equivalence checker uses a symbolic proof to verify that the functionality remains the same. The proof is exhaustive, meaning there is no need to simulate with a set of tests.
See this for more info.