which is the best possible way to perform Schematic vs Schematic for 2 Verilog gate-level codes?

I want to do Svs just like people do for LvL in case of layout vs layout. SvS is also available for spice netlist.

  • \$\begingroup\$ I'm not quite sure what you mean with "performing Schematic vs Schematic"? \$\endgroup\$ – Marcus Müller May 12 '18 at 12:49
  • \$\begingroup\$ A schematic diagram is just a graphical representation of a netlist, so I don't understand what distinction you're making between the two of them. \$\endgroup\$ – Dave Tweed May 12 '18 at 13:30
  • \$\begingroup\$ Welcome to EE.SE! Keep in mind that questions about optimization require a definition about what problem dimensions are to be optimized for your application, such as size, speed, energy consumpation, user experience, etc. Since these can't be optimized all at once, you need to have a good idea of which ones are most important to you, and be able to articulate that clearly to us. \$\endgroup\$ – Dave Tweed May 12 '18 at 14:30

I think you are referring to what is called formal equivalence checking. When you make changes to a gate-level net-list to meet timing, loading, or any other optimization goals, an equivalence checker uses a symbolic proof to verify that the functionality remains the same. The proof is exhaustive, meaning there is no need to simulate with a set of tests.

See this for more info.

| improve this answer | |
  • \$\begingroup\$ Also look up yosys for a free formal verification tool for verilog \$\endgroup\$ – C_Elegans May 12 '18 at 20:58

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