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I tried to write VHDL code for a sync JK FF. I have the following error:

line 18 syntax error near if statement.

Could anyone explain to me what is wrong with the if statement?

Also, is this code okay? I tried looking on the internet, but haven't found code for a sync JK FF anywhere. By sync I understand that the reset should be synchronous with the clk?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity JK_FF is
Port ( J : in  STD_LOGIC;
       K : in  STD_LOGIC;
       R : in  STD_LOGIC;
       clk: in  STD_LOGIC;
       Q : out  STD_LOGIC;
       QB : out  STD_LOGIC );
end JK_FF;

architecture Behavioral of JK_FF is
   signal M: STD_LOGIC;
begin

process (M, J, K, R, clk) 
begin
   if (clk'event and  clk = '1') then   
      if (R = '1') then 
         M <= '0';
      end if;
   else
      if (J = '0') then
         if (K = '0') then
            null;
         else
            M <= '0';
         end if;
      else
         if (K = '0') then
            M <= '1';
         else
            M <= not(M);
         end if;
      end if;           
   end if;
   Q <= M;
end process;

end architecture;
end Behavioral;
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  • 1
    \$\begingroup\$ Shouldn't it be "not M" rather than not(M)? Link \$\endgroup\$ – Andy aka May 13 '18 at 13:17
  • 1
    \$\begingroup\$ Which "if" statement? There are many, all badly formatted. Fix the formatting and you'll probably see the error right away. (And most of the parentheses are harmless but unnecessary clutter, not just around M in Andy's comment. (Your process has no "begin" so "if" is confusing the parser) \$\endgroup\$ – Brian Drummond May 13 '18 at 13:28
  • \$\begingroup\$ tried to change the code but I have more and more errors as I do.Could you please tell me where I could look for a VHDL code for JK FF as I searched but only found for asynch. The thing is I managed to work it out for the other FF but I'm not sure how to for JK,thank you \$\endgroup\$ – Lola May 13 '18 at 14:00
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    \$\begingroup\$ Also, are you sure this should be doing what you want it to be doing? The process sensitivity list should only contain the clk, and R, if R is supposed to be an asynchronous reset. What you have there is the whole JK business ran whenever there isn't a clock signal? Why? How would that even synthesize? \$\endgroup\$ – Richard the Spacecat May 13 '18 at 14:17
  • 2
    \$\begingroup\$ "Could you please tell me where I could look for a VHDL code for JK FF" - I left a thing called a L I N K in my comment. Try that and report back and please try and read comments carefully. \$\endgroup\$ – Andy aka May 13 '18 at 20:10
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  1. Process senstivity list should contain only "clock", since its synchronous FF.

  2. end behavoral is enough. No need of end architecture

  3. your first end if should be at the end.

  4. Your Q is delayed by one cycle, so use variable. You missed QB as well.

  5. Try to use elsif to improve readability, instead of else and using if inside else.

  6. Intend your code always.

useful link

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