I tried to write VHDL code for a sync JK FF. I have the following error:
line 18 syntax error near if statement.
Could anyone explain to me what is wrong with the if statement?
Also, is this code okay? I tried looking on the internet, but haven't found code for a sync JK FF anywhere. By sync I understand that the reset should be synchronous with the clk?
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity JK_FF is Port ( J : in STD_LOGIC; K : in STD_LOGIC; R : in STD_LOGIC; clk: in STD_LOGIC; Q : out STD_LOGIC; QB : out STD_LOGIC ); end JK_FF; architecture Behavioral of JK_FF is signal M: STD_LOGIC; begin process (M, J, K, R, clk) begin if (clk'event and clk = '1') then if (R = '1') then M <= '0'; end if; else if (J = '0') then if (K = '0') then null; else M <= '0'; end if; else if (K = '0') then M <= '1'; else M <= not(M); end if; end if; end if; Q <= M; end process; end architecture; end Behavioral;