Switching analog and digital inputs to uP

Question

I have a microcontroller, which requires that no signals are connected to its input ports during startup. There is a control signal SYS_RESET, that should first rise, before any input is connected to the uP's expansion headers. As a result, I am looking for a way to use this SYS_RESET signal as an enable signal, to efficiently switch all the input signals. The choices I am considering are tri-state buffers, multiplexers, and electronic CMOS switches.

What I am looking for is a single IC, with many channels (the more the better, the BBB has around 40 GPIOs, and 7 AnalogIns) that are all controlled by a single enable signal. Also I need a through-hole package. Any suggestions?

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I am using the beaglebone black wireless. What I am referring to in the question above, is found in this link at the "tips and pointers" section, "expansion headers pin usage" subsection, the points 1 through 5 (especially point 3).

1. Do not apply any voltages to any I/O pins when the board is not powered on.
2. Do not drive any external signals into the I/O pins until after the SYS_RESETn signal is HI (3.3V).
3. Do not apply any voltages that are generated from external sources until SYS_RESETn signal is HI.
4. If voltages are generated from the VDD_5V signal, those supplies must not become active until after the SYS_RESETn signal is HI.
5. If you are applying signals from other boards into the expansion headers, make sure you power the board up after you power up the BeagleBone Black or make the connections after power is applied on both boards.

I am also posting the datasheet of the BBB

Answer 1

I don't use the BeagleBone range of boards, but I've done some research on the general topic of your question (despite the original question being a shopping-type question, which doesn't fit the rules of the site) and found what I hope will be helpful for you. In summary:

1. The recommendations whose link you gave in your update, are genuine. They seem to be related to the fact that the BeagleBone Black Wireless you have (and other members of the BeagleBone family) use microprocessors with multiple power rails, and not what most people would call microcontrollers, which tend to be simpler devices with usually only a single power rail.

   The BeagleBone Black Wireless uses the Octavo Systems OSD3358 SOC, whose main component is the TI Sitara AM3358 processor but includes many other components too, including the power management IC (PMIC) for the processor, which controls the power-on sequencing of the processor's multiple power rails.

   Section 5.1 (Absolute Maximum Ratings) on page 80 of the current version of the TI datasheet for the AM3358 says:

   Steady state max voltage at all IO pins
   ...
   –0.5 V to IO supply voltage + 0.3 V

   and then in a footnote it says:

   This parameter applies to all IO terminals which are not fail-safe and the requirement applies to all values of IO supply voltage. For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –0.5 to +0.3 V. Apply special attention anytime peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences. [my bold]

   and also says:

   Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. The USB0_VBUS and USB1_VBUS are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the steady state max. Voltage at all IO pins parameter in Section 5.1. [my bold]

   From the BeagleBone Black Wireless schematic and various datasheets, my research is that the SYS_RESETn signal (also called SYS_RESET# on some diagrams) is the most easily accessible signal to indicate (indirectly) that the PMIC has powered all of the processor's power rails, and then released the processor's reset signal (i.e. SYS_RESETn) to allow the processor to boot. If you don't "respect" that signal, to confirm that the processor's power rails are all powered before applying an external voltage, then you could break the requirements stated in section 5.1 of the AM3358 datasheet that I quoted above and, in the worst case, damage the processor.

2. After further research, I found your question has been asked before, on other types of BeagleBoard (which have the same requirement, as they share the same TI CPU family). For example:

   How to prevent applying power to I/O pins before BBB ready?

   and

   How to disconnect voltage from BeagleBone Black expansion pins?

   An answer on this question suggests using the TI SN54CBTD3384 bus switch. However if your input signals are above 3.3V then, personally, I don't recommend that device in this application, without more research into its claimed level-shifting, due to the warning in the datasheet:

   In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting effect.

   Also the SN54CBTD3384 is being discontinued in the DIP package which you wanted, and I couldn't find it during a quick search of the usual distributors. (That's a good example of why shopping questions are discouraged - they become out of date, as has happened with that answer.) Instead you might consider the SN74CBTD3384 version, but apparently that doesn't come in a DIP package, so you would need to buy something like the SOIC package and use an SOIC-to-DIP adapter board, if you really need a DIP package device.

   Of course other bus switches are available and should be considered. Instead of limiting yourself to DIP package devices (which will become rarer over time, due to lack of market demand) consider using a (relatively) easy-to-hand-solder SMD package (like SOIC) and an adapter PCB, as I mentioned above.

   In theory, rather than gating several I/O signals using bus switches, driving a single power-enable signal from your BeagleBone board, to the external power supply of whatever is driving the I/O signals connected to your BeagleBone board, might be possible with some system designs. That way, the external device(s) would only be powered after the BeagleBone is already "up".

   However, ensuring that the external devices lose power before the BeagleBone board during a power-down would require careful design e.g. considering "surprise" power removals from the BeagleBone board and the output capacitors in the power supply for external devices, which may keep that external voltage present even after the BeagleBone board has lost power.