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For the below image, howcome assign out = a&~sel + b&sel only outputs one instead of the ref solution below? Is there any way to do this problem with assign only?

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enter image description here

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Looks like I'm too new to comment here, but I wanted to expand on the previous answer. With one-hot mux selects, that you want to synthesize into an and-or tree, you can't use the ternary conditional operator. You have to use the replication operator. This is one thing that vhdl (I think) does better than verilog.

assign foo = in1 & {WIDTH{sel1}} | in0 & {WIDTH{sel0}} ;

If the original questioner tries something like this to replicate the select, it should work. But ternary conditional is preferred. So is if/else inside an always block.

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Could that be because the sel is just one bit wide?

If you wanted to use that, you'd probably have to extend the sel to the same width as the other inputs.

Quite frankly, I don't know why'd you want to do it that way (the (a & ~s) | (b & s) way), really. Just use the ternary operator as suggested - it really is easier to read and less cluttered. (Sure it may be confusing at first, but you'll get used to it quickly.)

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