I am reading the datasheet of SX1301. I got struck at
SX1301 RX operation using a third party RF front-end topic (Page 22). The page (22) says:
In that mode the SX1301 expects a stream of 4 bits samples at a 32 MSps rate. The “Sample valid” input should pulse every 8 clock cycles to delimit packets of 8 samples. From those 8 samples representing 32 bits, the first 24 MSB are kept as I/Q 12bits sample information and fed to the internal sample 4 MSps sample bus.
and in the next page, they have written:
The RF front-end must provide a 32 MHz clock. ”Sample valid” and data bits must change state on the rising edge of the clock. They are sampled internally in the SX1301 digital IC on the falling edge of the 32 MHz clock.
There are only two pins to transfer samples to SX1301 from
RF Front End (A_IQ_RX and A_QI_RX pins) and they have mentioned above that One sample is of 4 bits and 1 clock cycle transfers one sample. How can they transfer 4 bits in one clock cycle.
The data (I/Q samples) are transferred once (falling edge) in a clock cycle. How is it possible to transfer 4 bits then considering transferring occurs once each clock cycle?