I have a design that relies heavily on internal dual port RAM found in the FPGA and I want to take advantage of the fact that blockram can have power-on initial values to populate all this memory with random data. How I plan to do this is to make a named pipe through a pre-synthesis TCL script, pump random data into it and have it read by a VHDL function. I've seen similar things done, only with text files.
My question is, doing it this way, will all instances of the blockram module be filled with the same pseudo-random data, or will each be synthesised "separatedly" somehow, ending up with different pseudo-random data, which is what I'm after?
The tools are Vivado 2015.4 and the part is Zynq-7000 (7-series Xillinx FPGA), by the way
I've seen people reading block ram initial content from a text file in VHDL and the result is synthesisable. I want to do something similar, but rather than a plain text file, I'm thinking of using a named pipe with the write end connected to a bash script to generate random initial blockram content in the bitstream. However, I'm not sure exactly what the synthesis tool does with the block ram module: is each instance of the same VHDL design file synthesised in one pass, making the RAM content of all repeated instances identical, or are they treated separately, thus populating them with different random data?