# How to amplify the output of an on NMOS, connected to zero source voltage?

I am simulating a 3 transistor based XNOR cell using HSPICE. The circuit is shown in the picture.

technology = 45nm

Vdd=1.1v

|Vth|=0.62v

In the case of A=1 and B=1, the output is charged through the N1 transistor. You know NMOS passes the Vs=Vdd to its drain as Vdd-Vth. The problem is when Vth>Vdd/2, the drain voltage becomes less than Vdd/2 and it is assumed as approximately zero, while the desired output is Vdd. So, if I connect this output to the gate of a PMOS, it will be turned on, which is not the desired case.

I want to amplify this output using few transistor and no resistances, just the case A=1 and B=1, to become close to Vdd. How is it possible to amplify this output?

Thanks

simulate this circuit – Schematic created using CircuitLab

The simplest way to amplify digital signals is adding inverters. If an inverted output is not allowed, you can add 2.

You have some control over the switching threshold by playing with the w/l ratios. Make sure your NMOS has more beef than the PMOS to have a low switching threshold.

Downsides are possibly an increased area and/or propagation delay.

Alternatively, you can also move to a different XOR circuit that doesn't need a switch to work.

If you have both inputs and their inverted signals, you can also use

You can probably find more.

• I have played with w/l ratios so much, however, the result is too low. I connected the source of N1 to an inverter, connected to the gate of a pmos with its source equal to B. I could amplify the output from 0.355 to 0.720. However, still the xnor output is considered as low when I connect it to a pmos. :( – Arghavan M.hasani May 16 '18 at 16:00
• I guess that means you don't have enough headroom to use that circuit then. I suggest going to a different XOR or XNOR circuit. I'll update my answer with some examples. – Sven B May 16 '18 at 18:00
• Is the technology effective in this output? I have found the design in a paper using 0.35micro technology while mine is 45nm. ok I will try another circuit like the first you proposed. I want to use as few transistors as possible. If you can help me more, I would be very appreciative. – Arghavan M.hasani May 16 '18 at 19:57
• I've used 0.35um myself, and they usually use a 3.3V supply or sometimes 1.8 if possible to save power. Did they also use 1.1V in the paper? – Sven B May 16 '18 at 20:26
• They have simulated a range of vdd from 1.8v to 3.3v. However, I have to work in 45nm. For the first circuit which you proposed, we have the same problem when A=0 B=1. What should I do? :( – Arghavan M.hasani May 16 '18 at 20:31

I changed this XNOR cell to an XOR cell with 4 transistors and a simple circuit to amplify Vdd-Vt in the case A=0 B=1. The first XNOR cell has high leakage and power in 45nm, though it has few transistors.

simulate this circuit – Schematic created using CircuitLab

Here is the new circuit