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I'm a newbie to VHDL and I'd really be grateful if someone could help me solving this question which has been bugging over the last few days. I don't have a code for this. Assuming, if there's a code layout, like below, which does something when it sees rising edge of the clock.

PROCESS(clk) BEGIN IF(rising_edge(clk)) THEN --functionality END IF; END PROCESS;

Eventually, at the falling edge of the clock, what would this kind of code do? Will be there any activity? How would the power consumption look like during the falling edge?

Thank you in advance!

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You haven't programmed anything to happen on the falling edge, so nothing should happen, no change of logical state, to any of the signals, latches, outputs you have defined.

However, there will still be activity on the clock net, capacitances to charge, so there will be dynamic power consumption.

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  • \$\begingroup\$ Thanks a lot! One small question though, since you mentioned there'd be dynamic power consumption, is it due to both charging as well as short circuit current? \$\endgroup\$ – Vignesh Ramakrishnan May 16 '18 at 14:15
  • \$\begingroup\$ @VigneshRamakrishnan What short circuit current had you in mind? \$\endgroup\$ – Neil_UK May 16 '18 at 16:45
  • \$\begingroup\$ Short-circuit current that I had in mind was the one when both P-MOS and N-MOS are conducting. So, will this be of any reason for Dynamic Power Consumption (DPC)? Also, I've another quick question. If my VHDL code consists of a combinational logic as well as a register update for every clock (sequentially) within the PROCESS statement then would there be a difference in DPC between combinational logic and register update when synthesized? \$\endgroup\$ – Vignesh Ramakrishnan May 17 '18 at 5:43
  • \$\begingroup\$ @VigneshRamakrishnan If there is shoot-through (what your short circuit current is more generally known as) then dissipation will occur on a per-edge basis, so will scale like DPC with clock frequency. If you have combinatorial logic, then it should be independent of the clock, and of falling clock edges. Its DPC will be based on how fast its inputs and uotupts change, not on the clock. \$\endgroup\$ – Neil_UK May 17 '18 at 7:54
  • \$\begingroup\$ Ah, now I get it! Thank you so much for the help :) \$\endgroup\$ – Vignesh Ramakrishnan May 17 '18 at 8:21

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