I'm a newbie to VHDL and I'd really be grateful if someone could help me solving this question which has been bugging over the last few days. I don't have a code for this. Assuming, if there's a code layout, like below, which does something when it sees rising edge of the clock.
Eventually, at the falling edge of the clock, what would this kind of code do? Will be there any activity? How would the power consumption look like during the falling edge?
Thank you in advance!