I want to interface 3 separate ADS8548 ADC with XC3S200AN fpga. The fpga masters the control lines of the ADCs and it also acquires the digital data from the ADCs through parallel bus.
I will have to acquire data from all three Adcs simultaneously. I am a beginner when it comes to VHDL and I have no idea on the time span of the data acquisition.
What are the things I will have to consider in VHDL to make sure that all three Adcs are controlled effectively and data is acquired without any time lag between one another.
Replies in terms of Logic blocks in the code and example code for ADC data acquisition will be really helpful.