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I want to interface 3 separate ADS8548 ADC with XC3S200AN fpga. The fpga masters the control lines of the ADCs and it also acquires the digital data from the ADCs through parallel bus.

I will have to acquire data from all three Adcs simultaneously. I am a beginner when it comes to VHDL and I have no idea on the time span of the data acquisition.

What are the things I will have to consider in VHDL to make sure that all three Adcs are controlled effectively and data is acquired without any time lag between one another.

Replies in terms of Logic blocks in the code and example code for ADC data acquisition will be really helpful.

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You'll have to supply a pulse to CONVST_A, CONVST_B, CONVST_C and CONVST_D for all three ADCs to start their conversions. Use an external clock (XCLK) to synchronize the conversions. Check the BUSY/INT output for end-of-conversion:

When bit C27 = 1 (BUSY/INT in CONFIG), this pin is an interrupt output. This pin transitions high after a conversion has been completed and remains high until the next read access. This mode can only be used if all eight channels are sampled simultaneously (all CONVST_x tied together). The polarity of the BUSY/INT output can be changed using bit C26 (BUSY L/H) in the Configuration Register. (page 16)

You then can read the data of the different ADCs into several registers. At that moment timing is no longer relevant to the synchronicity of the conversion.

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  • \$\begingroup\$ I didnt know that xclk is used to synchronise all three adcs. thanks for pointing out. In my case, I will have to control the position of a unmanned vehicle based on the data from accelerometers placed at several points on the vehicle. i have chosen a lpc controller to communuicate these to a MCU(motor control unit). so reading the data into several registers and processing all these at the same time is time critical isnt? would you like to respond to it? also, please help me with vhdl code for data acquisition that I can have a look on and get few thoughts before I start my own. \$\endgroup\$ – V V Rao Aug 10 '12 at 4:01
  • \$\begingroup\$ @Vicky - Sorry, no VHDL experience, so I'm afraid I can't help you there. How time critical the data acquisition and processing will be will depend on the speed of the vehicle's motion. I think the most important is that the ADCs are synchronized, so that their data is correlated. If the vehicle moves only slowly the calculations time will be less critical. \$\endgroup\$ – stevenvh Aug 10 '12 at 6:18
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Your best bet, in my opinion, is to set up 3 sets of SPI lines on the FPGA. One for each IC. Share the clock line like stevenh said. Make an SPI block, configure it as a master, and have it communicate with a single slave. Then start a schematic file. Put 3 of your SPI blocks on the schematic. Build a new block to act as a controller. Use a state machine to start start the transmission and have it lock the values from the ADC in once the transmission is complete. You can use that block to distribute the values to the blocks that do the processing. Remember, VHDL is a concurrent language. If you've been programming in C for a while, it's going to take a little bit to get your mind from sequential to concurrent mode.

Since you didn't say what sort of digital experience you have, I would recommend this book. http://www.pearsonhighered.com/tocci/ There are tons of VHDL examples of all the building block digital circuits.

If that's not enough information to get you started, I'll draw something up later.

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