Simulation of a class E power oscillator using LTspice

My goal is to understand and design a class E power oscillator. To this end, I am trying simulate the following schematic using LTSpice. Circuit topology and the design values are extracted from the paper "from here" -

design specifications used in the paper are; Pout =1W, Supply =4.5V, frequency 800kHz, RL=50ohm, QL=13, efficiency =90% Objective of this question is not to understand the paper, but to understand why my repeat simulations does not work - of course, I believe that the circuit should work fine with their values. But to make the question clearer, in this paper, the circuit is modeled using its equivalent impedance sections (assuming only the fundamental harmonic) and the component values are calculated by using class E design equations for 0.5 duty. Few things to note: In their analysis, the the gate-to-source impedance of the MOSFET, Zgs was measured at 800 kHz and used for the analytical equations, and voltage divider is experimentally tuned to obtain 0.5 duty.

(differences from the original paper are 1. make R2 170k -> 150k because it was not producing the oscillation when R2=170k, 2. zener diode model was not given in the paper)

However, I the oscillation waveforms are follows. Which include Drain Voltage - V(D); Gate voltage - V(G), Voltage across RL - V(RL+) and supply current - I(V1)

What could be the reason for this oscillator not working as expected? (It is expected to deliver approximately 1W power to RL, but here it is only few milliwatts)

Alternatively, can someone suggest any other reference (preferably open access) to design a class E power oscillator close tho the same design specs?

• You can only view the original if you are an IEEE member. Are you wishing answers to be restricted to those people? Mark the nodes you measured on your schematic too. May 17, 2018 at 12:14
• Looks like the first job is to find the LF resonance and kill it. What does the paper say about L3 and Cgs/Cgd?
– user16324
May 17, 2018 at 12:34
• Andy if you copy the IEEE title, you can locate elsewhere (sometimes) May 17, 2018 at 12:35
• C3 and Cbp are uselss. If you want them to be active, impose 4.5 Rser=10m (for example) in V1. Better yet, make it 4.5 Rser=10m Cpar=1u. May 17, 2018 at 12:59
• Whenever I see paper with reactive parts that use 4 digit values, I expect the design to overlook many sources of error. This osc must have enough gm or gain to overcome the C ratio attenuator. You have a 71kHz Osc. I wonder what your layout looks like May 17, 2018 at 13:06

and some details for the waveforms as in your example. Note that V(x) is V(RL+), and I used parasitics for the supply, which means the current through it incorporates what would have been your capacitors (if you had some resistance between the supply and the caps, as per the comment):
• @Pojj Those are subcircuits (i.e. more involved models), so I can't tell you what's wrong or not, I simply used a .model from LTspice's database. But I'd advise using different MOSFETs, even IRF has made newer, better ones than those, they're pretty ancient. May 17, 2018 at 14:56