I have been studying VLSI Design and cannot seem to find the difference between the two adder circuits below. Both implement the functionality of a full adder with Generate, propagate and kill conditions. Can anyone point out the difference?
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They are functionally identical. The only difference is in where the series-connected P-channel devices are connected at the top.
( Sorry, I'm on a touch screen device, and I can't mark up your figures.)
Note that on the upper left in the first diagram, the two series-connected devices for A and B are connected to the node with the parallel devices for A and B, which are then connected to Vdd.
In the second diagram, the same series string is connected directly to Vdd.
The same thing happens on the upper right with the series-connected string for A, B and Ci. In both cases, these connections are functionally identical (work out the truth table if you're not sure). It probably has something to do with optimizing the layout on the die.
answered May 18 '18 at 12:46
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\$\begingroup\$ Does it also have to do something with the fact that series pMOS transistors have a large resistance and cause more delay? \$\endgroup\$ – hacker804 May 18 '18 at 17:33
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\$\begingroup\$ Possibly. But then why would the first variation exist at all? \$\endgroup\$ – Dave Tweed♦ May 18 '18 at 17:46
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\$\begingroup\$ Because it is a direct static CMOS implementation created using a PDN and a complementary PUN whereas the second one is a modified and more optimized version. \$\endgroup\$ – hacker804 May 19 '18 at 2:41
