Please see the following code. (For the sake of clarity, it is a YCbCr 4:2:2 to 4:4:4 SerDes.)
always @(posedge clk_54, posedge reset) begin if (reset) cntr <= 0; else if (flag_in) cntr <= cntr+1; end always @(posedge clk_54, posedge reset) begin if (reset) begin Y <= 0; Cb <= 0; Cr <= 0; end if (cntr==0) Cb <= YCbCr; else if ((cntr==1)||(cntr==3)) Y <= YCbCr; else if (cntr==2) Cr <= YCbCr; end
The input clock is 54 MHz. cntr is a two bit counter. flag_in is a flag telling the counter when to start. It is very clear than none of the three output signals, Y, Cb, or Cr, change at a faster rate than 27 MHz (half of 54). If so, can I safely sample the signals at 27 MHz and not worry about clock domain crossing issues, setup and hold, etc?
I plan on synthesizing with Vivado and placing onto an FPGA. The 27 MHz clock will be derived from the 54 Mhz with Vivado clocking wizard.