Please see the following code. (For the sake of clarity, it is a YCbCr 4:2:2 to 4:4:4 SerDes.)

always @(posedge clk_54, posedge reset) begin
if (reset)
    cntr <= 0;
else if (flag_in) 
    cntr <= cntr+1; 

always @(posedge clk_54, posedge reset) begin
if (reset) begin
    Y  <= 0;
    Cb <= 0;
    Cr <= 0; end
if (cntr==0) 
    Cb <= YCbCr;
else if ((cntr==1)||(cntr==3)) 
    Y <= YCbCr; 
else if (cntr==2) 
    Cr <= YCbCr;

The input clock is 54 MHz. cntr is a two bit counter. flag_in is a flag telling the counter when to start. It is very clear than none of the three output signals, Y, Cb, or Cr, change at a faster rate than 27 MHz (half of 54). If so, can I safely sample the signals at 27 MHz and not worry about clock domain crossing issues, setup and hold, etc.?

I plan on synthesizing with Vivado and placing onto an FPGA. The 27 MHz clock will be derived from the 54 MHz with Vivado clocking wizard.

  • \$\begingroup\$ Are the 27 MHz and 54 MHz clocks asynchronous to each other i.e. from separate sources? If so, their phase can/will drift as their frequency ratio won't be a precise 2:1 and your 54 MHz input DFFs (which you should have) can go metastable as you will indeed be crossing clock domains. \$\endgroup\$
    – TonyM
    May 21, 2018 at 9:52
  • \$\begingroup\$ I mentioned in the question that "The 27 MHz clock will be derived from the 54 Mhz with Vivado clocking wizard." \$\endgroup\$
    – David
    May 21, 2018 at 10:00
  • \$\begingroup\$ Vivado clocking wizard is a GUI, familiar to those who have used it. Sticking with the actual circuitry, are you saying that they are produced from the same PLL and therefore phase-locked to each other? \$\endgroup\$
    – TonyM
    May 21, 2018 at 12:34
  • \$\begingroup\$ What I am saying is that the 54 MHz clk comes from outside the board, and the 27 MHz is derived from the 54 MHz clock using the Vivado clocking wizard using the PLL option \$\endgroup\$
    – David
    May 22, 2018 at 4:35
  • \$\begingroup\$ Again, you're describing the Vivado GUI actions, not the circuitry it creates, so let's forget about Vivado for now. If you want to answer just my comment question above, I can give you a clear answer on your domain crossing, don't bother if you don't want that though. \$\endgroup\$
    – TonyM
    May 22, 2018 at 8:13

1 Answer 1


This looks like a 54 MHz circuit, since you have no obvious control of the phasing of the two clocks. So long as the two clocks are synchronous, and all of the clk_27 to clk_54 paths are timed for 54 MHz, then there should be no issues with metastability or convergence.

If any of the signals are generated by different clock sources (even if they are phase locked), or pass off-chip through external connections, you will need to allow for the worst-case delay variation there too.


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