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I am new to FPGA and FPGA-SoC world. I have a DE1-SoC board. I am doing a project. Hardware design of the project contains a memory block which is initialized using .mif file. I know that we can use assigned address by qsys (platform designer) to control any block on FPGA side using ARM (Linux).

image that somehow explains the system

I want to change the content of the memory block in FPGA part using ARM part (With a software program) while the FPGA part is configured. How can that be done?

The HW system on its own works (it was tested and simulated), but the memory content cannot be changed after the HW system is configured. I have to change .mif file, compile and reconfigure the HW in order to change the memory content now. I think there must be a software solution for that which I don't know yet.

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  • \$\begingroup\$ Do not hesitate to comment if you have question regarding the question (if you need more information) \$\endgroup\$ May 22 '18 at 5:57
  • \$\begingroup\$ Memory file initialization, check... you want to change the memory "while" the FPGA is being configured? nope, not gonna happen... Do you, possibly, mean "after" the FPGA is configured? \$\endgroup\$
    – CapnJJ
    May 22 '18 at 6:21
  • \$\begingroup\$ Yes, I mean after FPGA is configured \$\endgroup\$ May 22 '18 at 6:26
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Second answer as the comments are flowing off the page....

First find out how the memory is configured:

  • Address range on the bus
  • Data width
  • Byte enables?

Then the best solution is to simulate accessing your memory.
You may have a problem there. I have used mainly Xilinx but on e.g. the zynq system you have to fork out a decent amount of money to get a simulation model of the CPU system.

Alternative is to build yourself a bus access module!
That is a simple behavioral module that generates AXI read and write cycles. It does not have to do all possible AXI transfer: just the basic single beat read and write.

If you plan to do any work with AXI it is time well spend as you can use it again and again. Other advantages:

  • You don't have to spend hours working through a manual how to connect/use it.
  • You can expand it in in due time to make more complex cycles.

Disadvantage: It may not be 100% AXI compliant and at some time you will have to find out if the bug you are having is in the module or in the test-bench.

You might want to look at this webpage where there seems to be a free AXI bus model.

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ok, well... How do you plan to change it? (somewhat rhetorical).. you have an ARM... is it part of the FPGA or an external interface (i.e. via pins)? Assuming its part of the FPGA, or even not, can't you write a SW program that understands the addresses? FPGA design, you do that, and you have a memory mapped address space (by design) that has a address relative to the ARM.. hopefully, something directly addressed for ease. Forgive me if I over-simplify this, but, I think this is just an ARM, and a memory, residing on the AMBA bus(?) ARM is Master, memory is Slave(?) that receives AMBA transactions via Slave, and then, via a protcol-bridge, satisfies the memory transactions (i.e. a transfer function) to put your new values in memory.... Maybe I am missing something?

can you post a design drawing?

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  • \$\begingroup\$ Yes, it has a soc containing FPGA and ARM, there is a bridge between them as you mentioned. And you are right, I am using ARM as a master and FPGA memory block as a slave. And it is possible to reach the memory block using the address of that block relative to ARM, I got it. \$\endgroup\$ May 22 '18 at 6:48
  • \$\begingroup\$ But the problem now is what should be data format that is sent to that address? \$\endgroup\$ May 22 '18 at 6:50
  • \$\begingroup\$ For example if the .mif file contains 300 rows of 90 (as well as memory block) bit long words, how should I send data for it? \$\endgroup\$ May 22 '18 at 6:51
  • \$\begingroup\$ ok, good... so, is this a SW problem or a HW problem? Sorry, had to ask, as it's the classic question :) you have an ARM SW program that addresses the memory to modify the contents... let's back up for a second. Have you simulated your FPGA design? Either directly to the memory without the ARM, or Instruction set simulation for the ARM? I think, step one is, simulation with the ARM eliminated, and make sure your AMBA bus transactions are translated properly... then, once satisfied, introduce the ARM again with your SW. Simulation is your friend \$\endgroup\$
    – CapnJJ
    May 22 '18 at 6:57
  • \$\begingroup\$ depends on your memory configuration... don't over-think this... memory that is 16-bits wide expects (typically) 16 bit data, and in your case, via AMBA. forget the ARM and make that work (make a TB component.. behavioral... for the ARM). \$\endgroup\$
    – CapnJJ
    May 22 '18 at 7:02

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