Looking for a clever solution (writing in Verilog)
Let’s say I have two 8 bit values, and each value has an 8 bit score, for a total of four inputs, and I want to combine the two values into one 8 bit value based on the scores. Hypothetically, the simplest way would be
However, it seems to me this is not “easily synthesizable” because of the division by values that are not powers of two.
Anyone have clever ideas to write a code that would serve this function that is synthesizable? I don’t have specific definition for this fusion in mind, but it has to be synthesizable. I am also ok with less possibilities to fuse the values, meaning that I am ok with say, only 128 ways of fusing the values