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I must have spent 20 hours on this question and still i have not prevailed with an answer.

schematic

simulate this circuit – Schematic created using CircuitLab

schematic

simulate this circuit

Every time i end up stuck with to many unknowns. So circuit 1 is the general circuit, circuit 2 is DC model, Circuit 3 is small signal model

So from the beginning.

  1. Assume saturation mode.
  2. Because drain current is given and gm, VGS(DC) can be accordingly be solved. Gm=1mS VGS(DC)=1.5 V
  3. Issue in DC analysis. when drawing DC model you short all small signal voltage sources. Now at Vin in the second schematic. does that get short circuited because somewhere behind that point there must most definitely be an small signal source. If it it short circuited the VGS DC value of 1.5 V is not possible.therefor presumably it must be left as an open circuit? to have a 1.5 VGS value? This delema would not be an issue if there was a cap in the diagram and then the Vin source. unfortunately not the case.
  4. Vout in dc analysis left as an open circuit
  5. Move to small signal analysis
  6. See working out in attatched image. KVL from Vin->R1-> Ground and KVL vin->R2->R3->ground applied. Not that Rin = Vin/Iin. Apply 1 V test voltage to Vin. coresponding I Test= 2x10^-6 A.
  7. Results in expression for R2 in terms of a constant and I2 and an expression for R1 in terms of I1
  8. From here? I'm not sure

enter image description here

enter image description here

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  • \$\begingroup\$ Your schematic is not showing a mosfet but an npn bjt. \$\endgroup\$ – Bart May 23 '18 at 8:35
  • \$\begingroup\$ Far out. Sorry. Yea should be an NMOs \$\endgroup\$ – Alex Chala May 23 '18 at 8:36
  • \$\begingroup\$ Why did you calculate the small signal behavior? Is there something in the question that relates to the AC behavior? \$\endgroup\$ – Sven B May 23 '18 at 9:08
  • \$\begingroup\$ You can relate R1 and R2 to Rin (which is given), in small signal mode. Thats the logic. \$\endgroup\$ – Alex Chala May 23 '18 at 11:06
  • \$\begingroup\$ Well I can tell that neither the gate or output should be biased to 0V for the DC solution. If the gate was tied to ground, you could never have a bias current through the NMOS (\$V_{GS} = 0\$). Tying the output to ground would not make sense either as there is a DC current flowing through the NMOS, that continues through R3. \$\endgroup\$ – Sven B May 23 '18 at 11:26
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In DC, we can find some useful equations by using the information about the transistor.

schematic

simulate this circuit – Schematic created using CircuitLab

$$V_{GS} = 1.5V = I_{R2}\cdot R_2 \Rightarrow I_{R2} = \frac{1.5V}{R_2}$$

The current \$I_{R2}\$ flows through \$R_3\$, along with the transistor's \$I_{DS}\$, giving another linear equation:

$$V_{OUT} = R_3\cdot (I_{R2} + I_{DS}) = 2k\Omega \cdot (I_{R2} + 0.5mA)$$

Finally, we also can bring \$R_2\$ into the equations by using that the voltages across all resistors need to add up to \$V_{DD}\$. Remember that the current through \$R_1\$ is the same as \$I_{R2}\$.

$$V_{OUT} = V_{DD} - 1.5V - R_1I_{R2} = 1.5V - R_1I_{R2}$$

As we are interested in \$R_1\$ and \$R_2\$, we can eliminate \$I_{R2}\$ and \$V_{OUT}\$.

$$\begin{align} 1.5V - R_1I_{R2} &= 2k\Omega\cdot (I_{R2} + 0.5mA) \\ \Rightarrow 1.5V - \frac{R_1}{R_2}1.5V &= 2k\Omega\cdot \left( \frac{1}{R_2}1.5V + 0.5mA \right) \\ \Rightarrow R_2 - 3R_1 &= 6k\Omega \end{align}$$

In small signal analysis, assuming you have an input current of \$i_{in}\$, you can find the input impedance using the following KCL equations:

schematic

simulate this circuit

$$ \begin{align} \left( \frac{1}{R_1} + \frac{1}{R_2} \right)v_{in}& - \frac{1}{R_2}v_{out} &=& i_{in} \\ -\left( \frac{1}{R_2} + g_m \right) v_{in}& + \left(\frac{1}{R_2} + \frac{1}{R_3} + g_m \right)v_{out} &=& 0 \end{align} $$

(We don't need the KCL law for the output because it is "hidden" by the voltage-controlled current source, and we are only interested in \$v_{in}\$).

The input impedance can be found from these equations (while substituting \$R_3 = 2k\Omega\$ and \$g_m = 1/1k\Omega\$):

$$ \begin{align} Z_{in} &= \frac{v_{in}}{i_{in}} \\ &= \frac{R_1(R_2R_3g_m+R_3+R_2)}{R_2R_3g_m+R_3+R_2+R_1} \\ &= \frac{R_1(2k\Omega+3R_2)}{2k\Omega+3R_2+R_1} \end{align} $$

Leading to the final equation (\$Z_{in} = 500k\Omega\$)

$$\begin{align} (2k\Omega+3R_2+R_1)\cdot 500k\Omega &= R_1(2k\Omega+3R_2) \\ \Rightarrow 3\frac{R_1}{1k\Omega}\frac{R_2}{1k\Omega} &= 1k\Omega + 1.5R_2 + 0.498R_1 \end{align}$$

We now have 2 equations for solving 2 unknowns, which leads to the following quadratic equation (eliminating \$R_1\$):

$$\frac{R_2^2}{1k\Omega} - 1672R_2 - 4k\Omega = 0$$

Taking the positive solution will finally result into

$$\begin{align} R_2 &= (10\sqrt{6989}+836)\ k\Omega \approx 1672\ k\Omega \\ R_1 &= \frac{R_2 - 6k\Omega}{3} \approx 555\ k\Omega \end{align}$$

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