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I am a complete newbie to electronics, But here i go.. I am trying to make some super simple logic gates for now an AND gate. In this logic gate i want to show which out en inputs are high by using a led. I have tried the following schematics:

AND GATE:

schematic

simulate this circuit – Schematic created using CircuitLab
In this case i want leds D1 and D2 to light up when there respective switches are pushed down / make connection. And when both switches are down / make connection i want the output to be 5v and the output led to light up aswel.

But at the moment the inputs leds barely light up and the output led never goes on. What am i doing wrong here? All help and suggestions are welcome.

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    \$\begingroup\$ Move D1 and D2 to being parallel (from the output of the switch to ground) with their own inline current limiting resistors. They're likely limiting the current to your base too much. \$\endgroup\$ – Reinderien May 23 '18 at 7:36
  • \$\begingroup\$ Also, your load should be moved to the top collector. \$\endgroup\$ – Reinderien May 23 '18 at 7:38
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schematic

simulate this circuit – Schematic created using CircuitLab

I have annotated your schematic with the nominal voltages expected across LEDs and transistors and the resulting currents. However these are the values I start with, to estimate what I expect to happen in our circuit.

I have started from the top, subtracting out the fixed voltages (VLED, VBE, VCE) until I get to a current setting resistor R1, then I can estimate the current.

Red LEDs have nominal 1.8V across them, transistor VBEs 0.6V, VCE_sat 0.3V. Actual values would be different as the currents are so low- try the simulator feature.

Your transistors are emitter followers, and have gain of, lets say, 100, so the base current of the transistors will only be 1/100th of the emitter current 106/100 - 1uA

So I am impressed you can see D1,2 light at all.

Keep eating the carrots, they are obviously working


Obviously you can't have the D1,2 in series with the bases.

This arrangement is still flawed for an AND gate, as the base current of Q2 goes to the output, regardless of the state of Q1. It would works as an OR gate (Q1,Q2 E and C connected), but not an AND gate.

As a NAND gate, you would put the load in the collector.


Have a look at some datasheets for 74 series logic (7400) as the old datasheets for TTL,CMOS (and RTL) have the internal schematics.

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    \$\begingroup\$ Never, EVER modify a question in order to answer it. Your answer may contain errors, and it makes it impossible for anyone else to answer the original question. It's easy enough to make a copy of a CircuitLab diagram -- just edit the original, select all, copy, exit without saving, start your own schematic, paste. \$\endgroup\$ – Dave Tweed May 23 '18 at 14:04
  • \$\begingroup\$ @DaveTweed Actually the paste function doesn't work - yay for html based software, and the promise of run-anywhere. Lucky you if it works for you. \$\endgroup\$ – Henry Crun May 23 '18 at 21:09
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    \$\begingroup\$ Alternative procedure: Copy the special block of HTML code that represents the circuit in the question into your answer, then edit that copy of the circuit. CircuitLab always does copy-on-write, so the original will remain unchanged in the question. \$\endgroup\$ – Dave Tweed May 23 '18 at 22:02

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