Design a 1024 bit serial-in/serial-out unidirectional shift register using a 1K × 1 bit RAM with a data input Din, data output Dout and control input READ/WRITE'. You may assume the availability of standard SSI and MSI components such as gates, registers and counters.

I know how to design shift register using flip-flops but I don't know how to do it by RAM. Please explain how to design it using RAM and if possible please provide a good reference so that I know more about it.

  • \$\begingroup\$ So you want a 1024 bit digital delay line? \$\endgroup\$ – ratchet freak May 23 '18 at 16:37
  • \$\begingroup\$ Think about it this way: Each clock cycle you need to put a new bit into the RAM somewhere, and you need to take out the bit you put in 1024 cycles ago. Dual port RAM will make this much easier. \$\endgroup\$ – The Photon May 23 '18 at 16:41
  • \$\begingroup\$ Hint: Connect your serial input to \$Din_0\$ and the output to \$Dout_{1023}\$. Then connect \$Din_i\$ to \$Dout_{i-1}\$. Then think about the logic of how to play with the address lines and the R/W signal (yeah, assuming dual port RAM). \$\endgroup\$ – Eugene Sh. May 23 '18 at 16:41
  • \$\begingroup\$ @ratchet sir ,sorry I don't know about delay line... here, I want to design a 1024 bit unidirectional shift register using RAM..I only know how to design n-bit shift register using n flip-flops.It was a GATE 1991 question..I have searched on internet but I didn't get any reference for it that's why I asked here. \$\endgroup\$ – ankit1729 May 23 '18 at 16:43
  • 3
    \$\begingroup\$ Not everything has "references" sometimes an exercise is just asking you to think. \$\endgroup\$ – Eugene Sh. May 23 '18 at 16:45

Seemingly, you are essentially stuffing a 1x1024 FIFO.. assuming you want the data back in the same way you put it in (i.e. the delay line @ratchetFreak mentioned above). in general terms: receive a bit, write it to memory @address 0, receive the next bit write it to memory @address 1, and so-on (i.e. your received-bit counter is your address generator). Afterward, you can count back down using the same counter, thus generating addresses for the read. If you aren't writing all 1024 in prior to reading any/all back out, and they aren't read in the same order and serially too, there is more to do in terms of control.


For a fixed length FIFO, you'll have a single 10-bit counter to generate addresses. The first 1024 bits out will be uninitialized. For every read/write command (I assume the one input triggers both functions) increment the address.

  • \$\begingroup\$ Nothing about read/write activity or control, downvoting until substantially improved I'm afraid. \$\endgroup\$ – TonyM May 23 '18 at 20:29

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