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Design a 1024 bit serial-in/serial-out unidirectional shift register using a 1K × 1 bit RAM with a data input Din, data output Dout and control input READ/WRITE'. You may assume the availability of standard SSI and MSI components such as gates, registers and counters.
I know how to design shift register using flip-flops but I don't know how to do it by RAM. Please explain how to design it using RAM and if possible please provide a good reference so that I know more about it.
Seemingly, you are essentially stuffing a 1x1024 FIFO.. assuming you want the data back in the same way you put it in (i.e. the delay line @ratchetFreak mentioned above). in general terms: receive a bit, write it to memory @address 0, receive the next bit write it to memory @address 1, and so-on (i.e. your received-bit counter is your address generator). Afterward, you can count back down using the same counter, thus generating addresses for the read. If you aren't writing all 1024 in prior to reading any/all back out, and they aren't read in the same order and serially too, there is more to do in terms of control.
For a fixed length FIFO, you'll have a single 10-bit counter to generate addresses. The first 1024 bits out will be uninitialized. For every read/write command (I assume the one input triggers both functions) increment the address.
