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I am doing my first 6-Layer PCB with RF antenna connection tracks.

I am using this stack-up:

L1 Signal Layer

L2 Ground Plane

L3 Power Plane

L4 Signal Layer

L5 Ground Plane

L6 Signal Layer

I have some questions in my head:

  1. The power plane is splitted into 3 different voltages. As every signal layer has a reference solid ground plane close to it, it is not that important to cross power planes sections in signal layers because the return path will flow in those ground planes, right?

  2. In the bottom layer there are two antennas (one chip antenna and one ufl connector). In this case I think I should place a GND polygon pour in the bottom layer with many stitching vias to the ground plane, right? if so, is there any rule for placing those vias? (how many? where?) and what via size should I use? Should the polygon cover the whole PCB or just the zone containing the antennas?

A lot of questions, sorry! :)

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  • 1
    \$\begingroup\$ Are all the dielectric layers equal thickness? \$\endgroup\$ – The Photon May 23 '18 at 17:38
  • \$\begingroup\$ For the chip antenna, check the datasheet. Some of them need a ground plane, and some need an area entirely free of copper (in all layers.) \$\endgroup\$ – JRE May 23 '18 at 18:58
  • \$\begingroup\$ Partial answer but the rule of thumb for the vias is that they have to be less than 1/10 lambda of the highest signal frequency component apart. \$\endgroup\$ – hatsunearu May 24 '18 at 7:29
  • \$\begingroup\$ @ThePhoton: yes, all the thickness is the same for all dielectric layers. \$\endgroup\$ – jap jap May 24 '18 at 9:43
  • \$\begingroup\$ @JRE: yes, in my case the chip antenna needs clearance in all layers, but the datasheet says nothing about if placing a ground polygon pour is needed \$\endgroup\$ – jap jap May 24 '18 at 9:44

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