In DDR3, DDR4 DRAM ,I don't get the point that each column gives more than one bits?? Column decoder is also a mux which selects one of the bits in row buffer, and DRAM array is a crossed structure with each column is essentially a bit line. How could there be 4 or 8 bits per column??
Each "logical" column is actually implemented using multiple physical columns on the chip. When you ask for a burst transfer, the physical memory array inside the chip performs a single cycle, transferring, say, 64 bits all at once. Those bits will be serialized as 8 bytes over the external 8-bit bus in a DDR burst using 4 clock cycles.
Does this help?