In DDR3, DDR4 DRAM ,I don't get the point that each column gives more than one bits?? Column decoder is also a mux which selects one of the bits in row buffer, and DRAM array is a crossed structure with each column is essentially a bit line. How could there be 4 or 8 bits per column??

  • \$\begingroup\$ If you are talking about DDR3,DDR4 etc.. Modern CPU's use 64bit-bus because they use a 64-bit architecture so they will likely need the extra bytes.In DDR especially there are doubled bits/bytes per transfer because of the Double Data Rate \$\endgroup\$ May 24, 2018 at 14:21
  • \$\begingroup\$ Also the bus gets wider if you run Dual channel/ Quad /etc. RAM configurations. This Achieves greater bandwidth. \$\endgroup\$ May 24, 2018 at 14:28
  • \$\begingroup\$ Thanks for the remarks. I new about the DDR thing and bus width, rank , bank etc.. But multiple bits per column is where I am stuck!! \$\endgroup\$ May 24, 2018 at 14:31
  • \$\begingroup\$ You mean you you get more than one value with one set of coordinates? \$\endgroup\$ May 24, 2018 at 14:35
  • \$\begingroup\$ Yes exactly this is what the literature says. When you give a column address to coulmn decoder you get a byte or half byte. \$\endgroup\$ May 24, 2018 at 14:37

1 Answer 1


Each "logical" column is actually implemented using multiple physical columns on the chip. When you ask for a burst transfer, the physical memory array inside the chip performs a single cycle, transferring, say, 64 bits all at once. Those bits will be serialized as 8 bytes over the external 8-bit bus in a DDR burst using 4 clock cycles.

Does this help?

  • \$\begingroup\$ Thanks for your help. @Dave Tweed can you suggest me to some material that explain it in a little more detail with some figures?? \$\endgroup\$ May 25, 2018 at 6:20
  • \$\begingroup\$ Not really. My knowledge is mostly inferred from studying the chip datasheets (reading between the lines in some cases) and building memory controllers in FPGAs. \$\endgroup\$
    – Dave Tweed
    May 29, 2018 at 17:54

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