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I need to level shift a 26mhz 1.8v clock output by .7v on both the high and low side (so clock swings from .7v to 2.5v on output).

Would a simple diode/resistor setup like below work for this?

https://www.circuitlab.com/circuit/6v24nh/screenshot/540x405/

I did a simple circuit to simulate this, and it seems to shift the single nicely and clock output looks clean on scope, but its amplitude is shortened, so it swings from ~.9v to 2v, which I'm assuming is from the 1k ohm pull up I'm using. Some cutoff is fine, but how would I get this closer to 2.5v on the high?

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    \$\begingroup\$ Beware of rise time from diode capacitance and load capacitance and C ratios. dV/dt < 10%f unless phase noise matters. So try a BAT diode \$\endgroup\$ – Tony Stewart EE75 May 24 '18 at 17:37
  • \$\begingroup\$ M = mega, m = milli. \$\endgroup\$ – Andy aka May 24 '18 at 17:50
  • \$\begingroup\$ When you use the CircuitLab button on the editor toolbar you can save the image inline and you and the readers can edit or copy the schematic. \$\endgroup\$ – Transistor May 24 '18 at 22:55
  • \$\begingroup\$ You are going to have trouble getting a passive pullup to work at 26MHz. \$\endgroup\$ – Caleb Reister Oct 24 '19 at 6:42
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Something like this might be more predictable:

schematic

simulate this circuit – Schematic created using CircuitLab

I'm not sure if you actually 'require' a low of 0.7 V or you are just willing to accept it as part of the level conversion problem using diodes.

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  • \$\begingroup\$ Requirement is .7v-2.5v...(Its a normal 1.8v clock input, but the chips ground plane is shifted +.7v, and the signal source comes from a 0v ground plane...so if I directly connected the output the second chip would see the clock as -.7v-1.1v which would obviously not work). \$\endgroup\$ – electronuts May 25 '18 at 14:16
  • \$\begingroup\$ @electronuts Altered schematic ...you could simply adjust the resistive divider to get whatever high level you want. Since the risetime is dominated by 1/(R3+R4) it should be quite acceptable. \$\endgroup\$ – Jack Creasey May 25 '18 at 18:58
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Actually found an even better solution, instead of starting with clock output on the low side, I just reversed it, so took clock source from the high side (ie between .7v-2.5v and simply passed it through a 100nf capacitor, which brought it down to a 0-1.8v.

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  • \$\begingroup\$ What you did is AC couple the signal. That will work either way, as long as there is an appropriate DC bias on both sides and you can guarantee that the clock signal is DC balanced (high and low for the same amount of time). \$\endgroup\$ – Caleb Reister Oct 24 '19 at 6:36
  • \$\begingroup\$ Also, your capacitor may be a little large, I would try a 10nF cap and work from there. \$\endgroup\$ – Caleb Reister Oct 24 '19 at 6:39
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Here is good and working solution with only 3 devices (2 resistors and 1 nmos):

enter image description here
Simulation results show good transient switching and clean logic levels, even for 26MHz:

enter image description here

Regarding your circuit

You have to change the 5V to 2.5V!, and the 5V logic out is now 0.7/2.5V.

You can use this schematic. But I don't think you will get it run on 26MHz. Further the levels are dirty -> better use a push-pull stage.

D1 is a little bit strange. Seems that for the 5V version it limits the output voltage to 4V! In your case D1 is always in reverse operation. You can cancel it.

level shifter

Here is another circuit: maybe you have to clamp the output with schottky diodes to vdd and gnd, to get faster switching times.

schematic

simulate this circuit – Schematic created using CircuitLab

Hope it helps!

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Termination

At 26MHz, you don't want to cut corners. I mean this literally, since that's what passive pullups do. As you mentioned in your answer, placing a small capacitor in series to AC-couple the signal can work. However, there are a few caveats:

  • The signal must be DC balanced. If you have a continuous clock with a 50% duty cycle, this will not be a problem. However, you will have to use a DC-balanced encoding (such as Manchester or 8b/10b) in order to make this work for a data signal.
  • You need to provide appropriate DC biasing and termination at the receiver. In this case, I would suggest using far-end parallel termination. I chose a 100pF capacitor because it provides a 200MHz bandwidth, but you may need to experiment with different values.

schematic

simulate this circuit – Schematic created using CircuitLab


Use a level translator

Since you are dealing with a small offset voltage, you may be able to get away with using a logic level translator such as the 74LV1T34 or 74LV1T126. When powered from 2.5V supply, these devices should have input levels compatible with 1.8V LVCMOS, but output 2.5V logic. Just be aware that the low output will still be at GND, which may cause an ESD protection diode in your receiver to conduct.

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