# By-Pass Capacitors for my SIM7600 Module

I am designing a PCB for SIM7600 module. I am stuck at choosing right capacitors for it. The datasheet (Page 21 & 22) specifies the load transient of the module. You can found load transient below:

According to my calculations (considering the power supply is unable to supply transient), the capacitor should supply 1.154 X 10^(-3) Coulomb charge in 577 us (I X dt = 2A X 577us).

To calculate the capacitor value, I have divided charge required by max. ripple voltage (=300mV). The capacitor value (dQ/dV) came out to be 3.84 X 10^(-3) Farad. But the datasheet requires 1000uF capacitor if power supply is unable to supply the load transient. Am I doing it right?

I think I should consider the ripple current of the capacitor and ESR of the capacitor. Should I be selecting capacitor having ripple current more than 2A?

I have calculated max ESR by considering voltage shouldn't drop by 300mV while supplying 2A current. The max ESR obtained from my calculations is 0.15 ohm (dV/dI = 300mV/2A).

Am I calculating it the right way?

EDIT: I am using DC-DC regulator (AP6503). The load transient response of the regulator is:

It looks like my supply will be able to respond in a way that voltage deviation will be less than 300mV after 50 us of load transient. Do I need to use 50us time instead of 577us?

According to your DC-DC's datasheet, it is able to supply the current, so this is only about minimizing voltage drop due to fast transient currents. A switching converter can't react instantaneously to output current changes, so it is the job of the output capacitor to smooth out the peaks.

When the load current is stepped, several things occur:

• Current increases, and voltage drops according to the ESL of the output cap (L di/dt)

Since this isn't visible on your scope shot, then either your layout is good (ie, has low enough inductance), or the current rise time is too long. Don't worry about this, if you got a ceramic cap on the power pins of the module you're good. Can't get it any closer anyway, and there will be another cap on the module itself.

• Once the current has stabilized to its nominal value (here, 2A) the ESR drop is visible

The DC-DC has not acted yet, and not enough time has passed to discharge the capacitor, yet the output voltage drops by I * ESR due to Ohm's law. This looks like a step on the scope.

• Capacitor discharge

Drawing current from the output cap discharges it, so the output voltage looks like a ramp.

• DC-DC regains control

Once the switcher adjusts to the change, it brings the output voltage back under control.

All these phases should be visible on the scope. ESL is a spike, ESR is a step, Capacitance is a downward slope. You should do the test again at 10µs/div with a faster current step (if you use a current generator). This will make it clearer whether the cap needs more µF or less ESR.

If the ESR step already drops too much voltage, then it needs lower ESR.

However, if the ESR step is small enough, but you see the voltage ramping down too fast as the load current discharges the capacitor, then the ESR is good but this needs more µF.

Since you are concerned about the cap and not the DC-DC (which seems to work fine), most of the action occurs in the first 10µs of the current step, so you need to crank up the scope sweep speed. 100µs/div is useless.

I'm not going to recommend a capacitor type because it depends a lot on your constraints (height, cost, space, layout...) and also the temperature range. Some caps (Aluminium) have higher ESR when cold, so if this is intended for outdoors use in winter, make sure to check the ESR vs temp specs. Most solid caps (ceramic, solid polymer, etc) have stable ESR vs temperature, but those with wet electrolyte do not. So a safe bet would be a solid polymer cap (low ESR across temperature) of a few hundred µF. But it is not thin, so if you want it to be thin, you'll have to use lots of ceramics, or other low profile SMD caps.

• A great answer! I can imagine the details now at micro-second level! – abhiarora May 24 '18 at 19:28

If your power supply contributes no current during the 577 us period then using: -

$$I = C\dfrac{dv}{dt}$$

and re-arranging to: -

$$C = I\cdot \dfrac{dt}{dv}$$

Gives you a value of $C = 2 \times 0.000577 / 0.3$ = 3850 uF

Assuming the power supply can provide an amp during this period means the capacitance can reduce to a little over 1600 uF.

Should I be selecting capacitor having ripple current more than 2A?

You can use an electrolytic capacitor as the bulk energy provider and bypass it with (say) a 100 uF ceramic capacitor to handle the instantaneous requirements of the sudden load. This is best judged using a simulator for simplicity where you would use a bulk capacitor value of 3750 uF in series with its ESR and ESL all in parallel with a pure 100 uF capacitor. Micro-cap student version is free and so is LTSPice.

Your aim would be to make the ceramic capacitors value lower by experimenting with different ESR/ESL capacitors.

• That's what I have specified. What about ESR calculation? – abhiarora May 24 '18 at 18:13
• I have edited my question. – abhiarora May 24 '18 at 18:22
• And I have completed my answer. I don't like goal posts that move but if you want my opinion USE a sim tool and model the power supply droop as well as the capacitor ESR/ESL. – Andy aka May 24 '18 at 18:24
• One more question. I was looking for the Capacitors on Digikey. Looks like some of them don't supply max. ripple current. I am considering we need to calculate the max. ripple current by taking ESR in account, thermal resistance of the case and max. allowable temperature? – abhiarora May 24 '18 at 18:26
• Capacitors that don't specify ESR and ESL are wisely left on the shelf. Look for capacitors whose ripple current is specified at 100 kHz as these will have low ESL. – Andy aka May 24 '18 at 18:29

Consider I_Max/ V_pp ripple, and current rise time only to yield low ESR from GSM down to ESR of 4Vbat worst case when say at 3.2V near end of charge then end of life . It may start at 10kF, 25mOhm but end up at 1kF 250mOhm or so. So battery choice is part of the ESR vs f challenge. From 1ms to 0.1 ns for example.

Look at small case sizes with length/width ratios of 0.5 rather than 2:1 which has higher inductance on Murata or TDK site.

Most important is define ripple tolerance V and test/verify radio error rate rise with ripple and slew rate of ripple Then create a “design spec” for ESR vs rise time =0.35/f_-3dB then use this for carefully selecting array of C and ESR*C including battery spec. vs. SoC, state of charge and Vbat over lifespan .

Once you have this “spec” any experienced Engineer can compare solutions to specs. Finally beware high Q C’s interact to form disastrous resonance from step or impulses corrected by higher ESR compensation.

All radios are different and have some decoupling already. But this is the proper design motus operandi.

If not using a battery, but some Regulator they too have an ESR vs f that rises with f due to GBW loop limit and thus supplemented by ESR*C values on both inputs and outputs to extend the frequency range for Step load regulation error and impulse ripple.

Step Load Regulation error voltage = I(step){f,dt} * ESR {f,dt} meaning error is proportional to ESR and rise time and step size of current ( generalization)**