0
\$\begingroup\$

I want to know that my understanding about D flip-flops is right or not.

We have different types of D flip-flops:

  • Some of them are positive edged (0->1) and some of them are negative edged (1->0)
  • All of them take two inputs: an enable (clock) and another D input
  • They give two outputs: Q and Q'
  • For all of them, the output equals to the D input ( but they differ in the time of showing the correct output)
  • The Master-slave D flip-flop is a negative edged flip-flop.

Is this all true?

If not, what parts are wrong?

\$\endgroup\$
0
\$\begingroup\$

You are mostly correct. There is no requirement that a flip-flop have both Q and Q' outputs; a flip-flop may have just Q or just Q'. Both positive-edge and negative-edge triggered flip-flops are master-slave flip-flops...the only difference is that the internal connections to the clock and its complement are reversed. In general, an "enable" input is different from a "clock" input: a level-sensitive latch has an enable while an edge-sensitive flip-flop has a clock.

\$\endgroup\$
1
\$\begingroup\$

You basically have it right, but I think your not clear about a 'latch' type input, usually designated by 'LE', vs. and edge type input, either rising or falling edge.

'LE' is a carry over from the days when the CPU put out the address and the data on the same line. Address had to be first, and latched in place so the ALE pin on the CPU would hold LE high to make it transparent to address/data, then make it low to latch in the address it just put out. Now it can use the read/write pins with the address having already decoded the correct chip select (/cs) pins on the device the CPU is reading from or writing data to.

That is the key difference. LE = 1 means latch is transparent and data flows through it until LE = 0, then the address or data is frozen (latched in place.)

The 'D' type flip flop has tighter time constraints in that D must be stable with a 1 or 0 before the rising edge of a 74xx74 type flip-flop. The rising edge flip-flops dominate the market. The term 'flip-flop' is that if you wire /Q back to the 'D' input, it will toggle Q and /Q with every clock pulse.

This rising or falling edge must be fast or a sloppy unknown output could result.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.