I'm looking at prototyping a design I plan to build using logisim. The design will make use of a FIFO IC (74HC40105) as a buffer between a data producer process and a data consumer process. I can't seem to see a reasonable way of building the behaviour of the FIFO out of the basic components that logisim provides, however.
A shift register isn't quite right, because that requires the data to be fed in in advance to fill the buffer, whereas with the FIFO the data is available at the output after the first item is added; I don't need to wait for it to propagate through all the stages.
I considered simulating it using a RAM and read and write pointers to a circular buffer, but the downside with that is that (as noted in the description of this project which used the approach) you can't both shift in and out on the same cycle, which is because logisim's RAM only has a single address port, so can't handle true dual port simultaneous read and write (you could implement one this way in an FPGA, for example, because they usually support dual port RAMs).
Is there another way I haven't considered that would make it possible to implement a FIFO that lets both the data producer and consumer operate entirely independently in logisim?