I've spent a decade or two noodling around with logic gates on paper and in various simulators. By this point I think I have a good understanding of how to use them to build things. Now I'm interested in actually building real electronics with this knowledge. In theory, theory and practice are the same. In practice...

Question: How to real, physical logic gates differ from their theoretical cousins? What do I need to watch out for?

From my research so far:

  • Real gates take a finite amount of time to respond to their inputs ("propogation delay").
  • The exact propogation delay is not guaranteed to be the same for all the gates in the circuit.
  • Each output can only drive some finite number of inputs ("fan out").
  • "Unconnected" ≠ "logic low". Go get logic low, you have to actually connect to (−).
  • Unconnected inputs are catastrophically bad and will cause your soul to burn in agony for all eternity.
  • It is not possible to construct fast logic circuitry without a PhD in advanced electrical engineering and several billion dollars worth of specialist hardware.

Have I missed anything? What other traps await me?

  • \$\begingroup\$ Logic thresholds , breakdown voltage, latch-up ? \$\endgroup\$ – Long Pham May 26 '18 at 13:15
  • \$\begingroup\$ inter-chip propagation time, reflexion, meta-stability, power consumption, power decoupling, ground bounce, dead-on-arrival, stuk-at-X? \$\endgroup\$ – Wouter van Ooijen May 26 '18 at 13:56
  • \$\begingroup\$ PVT.... And, there are several more bullets to be had here... I feel like I could use one actually. And, as an aside... I will gladly get a phD if someone will pay me several billion dollars. \$\endgroup\$ – CapnJJ May 26 '18 at 13:56
  • \$\begingroup\$ And don't forget: the fact that nearly no-one uses separate gates anymore (for good reasons). Practical products use either a micro-controller or an FPGA. \$\endgroup\$ – Wouter van Ooijen May 26 '18 at 13:57
  • 2
    \$\begingroup\$ I would not agree that discrete gates are not used any more; certainly I do not build complete circuits out of them, but they have their place even with FPGAs and microcontrollers as plentiful as they are. If they weren't used, then they would not be available as freely as they are. \$\endgroup\$ – Peter Smith May 26 '18 at 14:19

The difference is mainly one of abstraction: digital gates are not simply on/off, they are really analog devices. The main abstraction, which you have alluded to, is that to a digital designer gates have no capacitance. This has two main consequences: gates switch immediately (no skew) and that you can drive an infinite number of gates with an output. As soon as you introduce capacitance at the gate, it takes a finite time for charge to accumulate and so there is a switching time and you can only connect to a small number of gates downstream (fan out) as you need current to charge the downstream capacitors.

This is true both internally to FPGAs/processors etc, and also to discrete gates. A full IC reduces the capacitance at the gates, and the distances, so can driven faster than a discrete circuit.

As mentioned in the comments, the time delay means there are scenarios in real circuits that you wouldn't see in a purely digital simulation. Meta-stability is one example, which occurs when signals do not meet setup and hold time requirements.

You do not need a PhD or billions of dollars, but a few hundred thousand would get you on the start line for an older process, say 130 nm. Experience is needed to actually layout ("tape out") the chip, and you need to run simulations at gate level to determine switching voltages, time differences etc. The simulation tools alone are very, very expensive in terms of licensing cost and processing power required.

  • 1
    \$\begingroup\$ Metastability is not due to skew between different signals, it's due to violating setup and hold times. When working with a single clock in a system, metastability is avoidable by respecting setup and hold times, which often involves controlling skew. When your system has asynchronous clocks, and a signal crosses from one clock domain to another, it is totally unavoidable, tsu and th will be violated, but the probability of a logical failure due to it can be designed down to a negligible probability. Metastability is much misunderstood topic. Please either delete it, or correct the cause. \$\endgroup\$ – Neil_UK May 26 '18 at 15:29
  • \$\begingroup\$ Fair point @Neil_UK, I was thinking asynch system, but not the fundamental reason. Will correct :) \$\endgroup\$ – awjlogan May 26 '18 at 18:30

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