So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, but I could synthesise and implement it with no warnings, and the real signals coming out seem to do what simulation made me think they would. I learned a few things along the way.
Now I want to learn how to set timing constraints and run timing analysis. So I am reading through the Xilinx doc UG612 and I see at the top of page 205:
"Use only one edge of the clock"
Hmm. Seems I broke the law. Part of my design is a parallel load shift register - I used the negedge of the last cycle of the clock to load it (from a counter which was clocked on the previous posedge). A quick sketch:
Of course, I am not directly using the negedge here, but the load signal is derived from it. I thought that this was good - but Xilinx tells me - don't do that.
Am I wrong? If so, why? What should I do instead?