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for my next project I need to implement a CRC IP core in Verilog HDL. It must use 16bit polynomial and 16bit CRC result register. Data is being fed into it in 8bit chuncks / bytes. I have allready implemented serial version of CRC core, using a shift register and xor gates, but I'm completely lost in how to do it in parallel, so that the result is available at the next clock cycle ?

Best regards

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There are a few ways to do this. In essence, what you need to do is 'unroll' the shifting part of computing the CRC so that it gets evaluated combinatorially within one clock cycle. One way to do this is with a for loop inside of a combinatorial block. If the polynomial is coming from a register (i.e. it can change at run time), then this is really the only way to do this. However, if the polynomial is coming from a parameter (i.e. determined and fixed at synthesis time) then you can compute what amounts to a matrix transformation that converts the previous CRC state and input data to a new CRC state and shifted output data.

Here is an example of some verilog code that implements the 2nd style, taking an arbitrary polynomial via a parameter: https://github.com/alexforencich/verilog-lfsr/blob/master/rtl/lfsr.v . That code forms the combinatorial core of a CRC module: https://github.com/alexforencich/verilog-lfsr/blob/master/rtl/lfsr_crc.v .

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