I'm using a dev board, the keil mcb4300. In the schematic, the audio codec UDA1380HN has the BCKI going to the SYSCLOCK.
According to the codec data sheet:
BCKI: bit clock input
SYSCLOCK: system clock 256fs, 384fs, 512fs or 768fs input
fs, is the sample frequency. If I am sampling at 8,000 samples per second, I assume that the lowest SYSCLOCK I can have is 256*8,000 = 2.048MHz.
According to the wiki on I2S, BCLK should be: frequency * word width * num of channels
In my case, that would be 8,000(Hz) * 16(bits) * 1(mono) = 128,000Hz
128KHz is not even close to 2.048MHz.
When I measure these settings on the scope, I see a 512KHz clock at BCKI. It is possible I have a higher sample rate than I think, and there is a firmware issue. In either case, it is working at a 512KHz clock. How is that possible? What am I misunderstanding?