I2S Clock in Audio Codec on dev board, how is this working?

Question

I'm using a dev board, the keil mcb4300. In the schematic, the audio codec UDA1380HN has the BCKI going to the SYSCLOCK.

According to the codec data sheet:

BCKI: bit clock input

SYSCLOCK: system clock 256fs, 384fs, 512fs or 768fs input

fs, is the sample frequency. If I am sampling at 8,000 samples per second, I assume that the lowest SYSCLOCK I can have is 256*8,000 = 2.048MHz.

According to the wiki on I2S, BCLK should be: frequency * word width * num of channels

In my case, that would be 8,000(Hz) * 16(bits) * 1(mono) = 128,000Hz

128KHz is not even close to 2.048MHz.

When I measure these settings on the scope, I see a 512KHz clock at BCKI. It is possible I have a higher sample rate than I think, and there is a firmware issue. In either case, it is working at a 512KHz clock. How is that possible? What am I misunderstanding?

Answer 1

Firstly you are probably NOT feeding the thing mono, the driver will be converting to a stereo bitstream, and for I2S I would bet the real word length is 32 bits (Possibly with only 16 or 24 of them having any meaning) and you are running the codec as a stereo part, in which case I make bclk 8000 * 32 * 2 = 512Khz which is what you are seeing.

Looking at pages 11 & 12 on the datasheet it is clear that the codec can produce a viable clock internally from a signal applied to the WSI input, which is likely what is going on here, it seems likely that the codec is acting as audio clock master using the WSI input as a reference.

Generally, even without this sort of thing audio clocking nomenclature within I2S and related things is a hot mess, SCLK/BCLK are both used as names, but the desired frequencies and meanings vary between vendors, very annoying.