# How can I size the 'supply noise filtering' capacitors at the load end for this scenario?

There is this SMPS dual-power supply which needs to power a load outdoors around 100 meters far away via a 3-wire cable as shown below:

simulate this circuit – Schematic created using CircuitLab

The load will draw max around 50mA but for a better signal quality some suggested to add caps at the load terminals to filter out the power supply noise.

I guess the way caps are placed correct, but is there a way to size the capacitors here? I need to find a logical explanation why we should use the capacitors with particular capacitance. Telling "I have seen somewhere it is a rule of thumb" does not convince some people. What should be the approach?

I would like to know for this application what value should be the capacitances of course and maybe even most importantly why.

• You need to fully define the load's input supply voltage requirements before this ship sails. And I'm not just talking about DC voltage limits but how it internally deals with line fluctuations across the spectrum of likely interferers. May 30, 2018 at 18:14
• Load's input supply voltage requirement is exactly +-15V. I don't know the internal circuitry of the load but here is a data-sheet for the load crlsensors.com/prodDocs/sa-120r.pdf May 30, 2018 at 18:24
• I thought 100u might short the power supply when turned on, so I need some sensible values at least. May 30, 2018 at 18:26
• If all you have is that the load requires +/-15 volts then you don't have enough information to make even a rule of thumb guess. May 30, 2018 at 18:33

I guess the way caps are placed correct, but is there a way to size the capacitors here? I need to find a logical explanation why we should use the capacitors with particular capacitance. Telling "I have seen somewhere it is a rule of thumb" does not convince some people. What should be the approach?

There are a few ways to do this:

1) Put in a large cap and a small cap with feelings (or the force or whatever). I usually use 1-10uf for 10-100mA of digitally switching current and under 1uf for 10mA (depends on what it is, and how fast its switching). maybe 100uf+ for 1A switching loads. This is what I get a feel for after reading lot's of datasheets over the years. If the microprocessor has many GPIO's that are switching on and off at the same time, then this could also be a problem. If the part is switching more than 10's of Mhz I'll also add a 0.1uf or few nf cap in parallel (or use an EMI 4 pin cap) to minimize terminal and PCB inductance. This is the leas time consuming method.

2) You can calculate it. The first number you need to know is the acceptable ripple on the Vcc line (or the minimum acceptable lowest voltage, on a 3.3V bus perhaps 3.2V would be a worst case voltage, depends on the part and datasheets). Then you find the max and nominal load and currents/loads. You estimate and calculate the cable and PCB trace resistance (and inductance if you think it will make a difference. There are wire and PCB trace available all over, or you could measure it)

You then solve this circuit with filter below. You start with the nominal current (if it's 50mA nominal current with a 5V Vcc then that's a 100Ω load. If the max current is 200mA then that would be a 25Ω load). You solve the circuit below with the switch thrown (which is something I don't have time to do right now) and calculate the max voltage drop, if it's too much increase the capacitor size until it falls in the acceptable level, doesn't sound like too much fun does it?

simulate this circuit – Schematic created using CircuitLab

3) You load the same circuit as in 2) into a spice package and solve it in 1 minute, or you load up a .param statement and solve for 5 decades of capacitor values and solve in a few more minutes. Packages like LT spice make it easy to put in parasitic resistance and inductance to make sure ripple is acceptable across all frequencies, with an AC sweep.

• Thanks a lot, I will read it and try to simulate and understand. As the current drawn increases the cap increases in your first examples. But let's say you decided to use 100nF after you made calculation and simulation ect., and someone insists to use 100uF; is there any serious disadvantage to use 100uF instead of adequate 100nF? May 30, 2018 at 20:08
• 100uf Capacitors have more ESR (equivalent series resistance) and more ESL (inductance) so they will not be able to filter higher frequencies as well. Which is why you put higher and lower values in parallel May 30, 2018 at 21:10
• I think u forgot to add a wire capacitance in your sim. Anyway, I know ESR will be high for 100uF but my question was: "100uF in parallel with 10nF" versus "100nF in parallel with 10nF" May 30, 2018 at 21:19
• Same goes for 100nF and 10nf, if you look at the ESL and ESR for bigger capacitors, it has to be higher because there is more material. There won't be much capacitance between the wires (less than pfs) and the capacitance in C1 is much larger so it could probably be neglected in most cases. May 30, 2018 at 22:43

You haven't told us about your load, but lets say it's a microcontroller. At every clock cycle, some transistors are going to switch and it's going to require a high current for a very brief period.

If you have no caps near your load, then all that current will have to travel the full loop to your power supply and back. The inductance of the loop is large, so the voltage will sag potentially causing glitches or other issues.

If you add these caps, then the brief bursts of current will be supplied by the caps, and the voltage will not sag. This is what decoupling caps are for.

Now, there are a few rules of thumb for which caps to use depending on your load, but you said you want to know why. Basically it goes like this. Each cap has an impedance graph that look like this:

Generally speaking, smaller ceramic caps will have a minimum impedance at higher frequencies, and large caps like electrolytics will have their minimum impedance at lower frequencies.

Now.. this graph is labeled in terms of frequency, but your current's not necessarily periodic, so it makes more sense to think of it in terms of edge rate (the rate at which your digital signals change). If you know that, then you can choose the right caps to get the lowest impedance, and therefor the lowest voltage sag.

In practice, it is almost always sufficient to just throw a 0.1uF cap on there. For high draw devices like motors you go larger (like 100uF), and for very fast devices with high edge rates you go lower (like 10nF), to get that that low impedance at high frequency.

• Is there a complication due to using 100u instead of 100n in my case? I have to be able explain why 100n is better than using 100u for this case in question. Load is here: crlsensors.com/prodDocs/sa-120r.pdf May 30, 2018 at 19:03
• The chart I posted is ceramic caps I think. If you overlaid some electrolytics on there you would see a similar impedance to the 2.2uF, but farther to the left. You'll need to either do some sims, or measure your device with a scope to see what "frequencies" you're actually dealing with. Once that's done just compare the impedance's between your options. Lower is better.
– Drew
May 31, 2018 at 3:32