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I am just doing some independent re-search for myself in audio amplifier (CHIP AMPS) such as the LM1875.

I want to learn more about how to compensate for audio chip amps and how their bode plot works and bandwidths, but in order to indulge on this I need to do some math to prove it to myself.

enter image description here

This is the LM1875 that I designed. Simply I want to just understand why C2 is used for as I have heard it's there to make your DC gain (22.2dB) flat among many frequencies which is true as shown here:

enter image description here

My idea was to make a transfer function of this op amp (Very simplify shown below) and just do a frequency analysis where s->jw and sweep it on the bode plot.

Here is my attempt:

Assuming this model now: enter image description here

Node VA = The voltage between the cap and the resistor.

First Node:

\$ \frac{V_{IN}-V_{OUT}}{R_{6}} + \frac{V_{A}-V_{IN}}{R_{7}} = 0\$

\$ V_{IN}(s)*[\frac{R_{7}}{R_{6}}+1]-\frac{V_{OUT}(s)*R_{7}}{R_{6}}= V_{A}(s) (1)\$

Second Node:

\$ \frac{V_{A}-V_{IN}}{R7} + C_{2}* \dot V_{A} = 0\$

\$ VA(s)*[1+R_{7}*sC_{2}] = V_{IN}(s) \$

\$ VA(s) = \frac{V_{IN}(s)}{1+R_{7}*sC_{2}} \$

Sub (2) into (1)

\$ V_{IN}(s)*[\frac{R_{7}}{R_{6}}+1]-\frac{V_{OUT}(s)*R_{7}}{R_{6}}= \frac{V_{IN}(s)}{1+R_{7}*sC_{2}} \$

Which comes down to:

\$ H(s)=\frac{V_{OUT}}{V_{IN}}= \frac{6.11s+1}{0.470s+1}\$

Bode plot:

enter image description here

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  • \$\begingroup\$ The TF is \$\large \frac{V_{out}}{V_{G1}}=\frac{1+C_2(R_6+R_7)s}{1+R_7C_2s}\$. But you need a balanced power supply, or lift the input signal above ground. \$\endgroup\$ – Chu May 30 '18 at 23:58
  • \$\begingroup\$ Would you mind explaining what you mean balanced power supply or lifting the input signal The transfer function is the same as mine? \$\endgroup\$ – Pllsz May 31 '18 at 0:00
  • \$\begingroup\$ You've got a negative sign in the TF. The output can't go more negative than the negative supply rail. If the input goes negative ... \$\endgroup\$ – Chu May 31 '18 at 0:04
  • \$\begingroup\$ Oh yes? I have an input circuitry that compensates for this? Using the voltage divider to bias the input voltage half of the supply, so it does go "negative" which is 0. The mapping is essentially 48 - 24 - 0 oppose to 24 0 -24 \$\endgroup\$ – Pllsz May 31 '18 at 0:05
  • \$\begingroup\$ OK, tidy up your diagram, then. \$\endgroup\$ – Chu May 31 '18 at 0:06
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In short, your circuit looks like this:

schematic

simulate this circuit – Schematic created using CircuitLab

As you can see your audio amplifier is supplied from a single power supply.

This is why you need a DC bias network. Because every "active device" to work properly as an amplifier supplied from a single source need proper bias circuit. When you use BJT as a CE amplifier, you use a voltage divider to bias the active device somewhere in the "linear region".

In case of single supply op-amp, you have to do the same thing. We need to bias the op-amp somewhere in the middle of his "linear region".

And this is a job for \$R_4,R_3\$ voltage divider. And this voltage divider "set" the DC bias at \$0.5 V_{CC}\$. We can say that this circuit sets the "virtual ground" for our opamp.

\$R_2\$ and \$C_7\$ were added to the circuit to improve the power supply noise rejection. Without it (\$R2 = 0\Omega\$) any "noise" present at supply rail will appear at the amplifier noninverting input and will be amplified by the amp thirteen times (\$1 + \frac{R_6}{R_7}\$).

In the same time \$R_2\$ resistor sets the input impedance of the amplifier seen by the input AC signal source.

Because the power opamp can also amplify any DC voltage present at the noninverting input the \$C_2\$ capacitor was added to address this issue. Without the \$C_2\$ capacitor, the output DC voltage will be equal to Vcc (0.5Vcc * 1+R6/R7). But we have this capacitor in the circuit, so DC voltage gain is reduced to one. And the output voltage is equal to \$0.5 V_{CC}\$.

Across opamp, we see a typical negative feedback network for a noninverting amplifier. Read this: How does this Op Amp affect voltage?

Additional \$C_4\$ was added to reduce AC gain at high frequency (above F > Xc4 = R5 ). \$F = \frac{0.16}{50pF * 12k\Omega} = 267kHz \$

The input network also looks typical for an AC coupling audio amplifier.

\$R_1\$ is a pull-down resistor when no input signal is connected.

\$R_2\$ and \$C_3\$ form an input low-pass filter (260kHz) to protect the amplifier from unwanted high frequency (RF) signals at the amplifier input.

\$C_{11}\$ is an input AC coupling capacitor and together with \$R2\$ forms a high-pass filter and set required low-frequency cutoff.

The output networks also look ordinary. And they are here to prevent high-frequency oscillations.

\$R_9\$ and \$C_5\$ form what is called a Zobel network.
The purpose of the Zobel network is to ensure that opamp output stage sees some "real"(resistive) load at very high frequencies.

Series L-R network (\$L_1,R_{10}\$) was also added to help ensure the amplifier will not oscillate at HF. At high frequencies, the impedance of the inductor (\$X_L\$) increases and isolates the opamp output from unwanted capacitive loads. And the \$R_{10}\$ resistor was added to damp the resonances that the inductor might have in combination with load capacitance at HF.

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  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. \$\endgroup\$ – Dave Tweed Jun 1 '18 at 17:19
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You are starting from a bit of a strange place. It is standard practice to run op amps from split supply rails (in audio typically +/-15 to +/-18V), and reference everything to the 0V which is obviously half way between the two.

It is possible of course to run these circuits from a single supply (for instance a 9V battery) but then there is always some kind of "hack" to create a mid-rail reference (which would be at 4.5V in this case). These workarounds are fine and work quite well (there are even special IC's for the purpose) but this is not the place to learn op amp fundamentals, because it does confuse the issue.

Regarding C2 in your circuit - it is not there to make "DC gain flat" as you say - quite the opposite. In audio, we typically do not want a flat frequency response to DC (or, the other way, up into the MHz region). There are good reasons to limit the bandwidth (keeping out RFI, pops and plosives from microphones, and so on) and well-designed systems have at least one -3dB point at either end - one typically at 10-20Hz, and another somewhere between 20kHz and say 100kHz or so (perhaps higher if marketing to people who believe in magic is a big concern).

Anyway, audiophile arguments aside, if we take a simple, standard non-inverting amplifier, without all the surrounding components and with no capacitors to control bandwidth (and no supplies shown, but remember that supplies of say +/-15V are there, and 0V is therefore in the middle of the working range):

schematic

simulate this circuit – Schematic created using CircuitLab

This has several important characteristics: 1. the input impedance is extremely high (many megOhms) 2. it is non-inverting. 3. the gain is given by (1 + R2/R1) (and therefore always > 1). 4. for the argument, let's say that this is an ideal opamp - so now we have "DC to light" frequency response. The gain part of the Bode plot is a straight line.

If we now place a capacitor in series with R1, we now that the the effective impedance from the + input to ground will now rise with frequency. If gain is high (R2 >> R1), the gain approximates R2/R1, and at the frequency where Xc = R1 we will be more or less 3dB down on the in-band. (A few minutes with a calculator will show that this is always an electrolytic with typically several 100uF value.)

By the same token, putting a cap across R2 increases the negative feedback with frequency, and hence reduces gain. Therefore, this is one of the standard methods for setting the upper -3dB point. (This cap usually ends up in the 100's of pF range, a ceramic or film type is usual.)

(In fact, I did a bit of hand-waving here to simplify the maths by assuming high gain which is not always the case. But it is quite often the case that the bandwidth limiting is done in a high-gain stage, as it also helps ensure stability. And given the poor accuracy of the caps used to do this, there is not that much point to be overly rigorous with the math.)

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  • \$\begingroup\$ Sorry what I meant about DC gain flat is that at low frequencies (0Hz) it doesn't amplify dc \$\endgroup\$ – Pllsz May 31 '18 at 17:14
  • \$\begingroup\$ then you mean DC gain is minus infinity. The amp blocks DC, and has no gain at all (there will be some very small gain at say 1Hz). Terminology is important. "Flat" in this context means a response that does not vary with frequency. \$\endgroup\$ – danmcb May 31 '18 at 17:17
  • \$\begingroup\$ I mean yea sorry about that, all I know due to the NFB at low frequencies any dc will be * 1 thus the same at the output \$\endgroup\$ – Pllsz May 31 '18 at 17:19
  • \$\begingroup\$ sorry, my bad. Indeed, gain is unity at DC for this circuit. \$\endgroup\$ – danmcb May 31 '18 at 17:24
  • \$\begingroup\$ Yeah exactly. Another question though do you know anything about how create the bandwidth of the op amp shown in figure 2 and creating zobel network? \$\endgroup\$ – Pllsz May 31 '18 at 17:26

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