Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.


simulate this circuit – Schematic created using CircuitLab

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of “in” is _.

My question is how can we calculate a number of states in above diagram. Is there any formulae for that or any logic to calculate?

  • \$\begingroup\$ 2 binary registers. How many combinations they can have? \$\endgroup\$ – Eugene Sh. May 31 '18 at 17:31
  • \$\begingroup\$ only 2 according to that. But if there are 4 combinations then the answer is 4 ? \$\endgroup\$ – Himanshu May 31 '18 at 17:33
  • \$\begingroup\$ How is it 2? Not really. Yes, it is 4. 2^2. BTW, if you look closer, you will identify a 2 bit SISO shift register here. \$\endgroup\$ – Eugene Sh. May 31 '18 at 17:33
  • \$\begingroup\$ If you can explain that supporting your answer. It will be really helpful thanks. \$\endgroup\$ – Himanshu May 31 '18 at 17:42
  • 1
    \$\begingroup\$ It can be 00, 01, 10, 11, right? Can you think why it can't be any of these? Can you think of anything else? \$\endgroup\$ – Eugene Sh. May 31 '18 at 17:46

Two FFs can be in a total of 22 = 4 states altogether. An appropriate pattern of bits on Input can drive the machine to any given state.

However, the actual question is more subtle than that: How many states can make a transition to a particular state?

The serial connection between the FFs implies that there's a limitation — what is it?


The Q output of first FF can be 0/1 and for each, the Q output of second FF can be 0/1. That gives a total of four states - 00,01,11,10. However, (correct me if I am wrong) both Q will have to be the same since both FF are activated by same edge of clock. In, other words the clock edge that enables first flip flop also enables the second flip flop. So I think we can only achieve the 00 or 11 states. A correct explanation is in comments.

  • \$\begingroup\$ No, this is wrong. Unless stated otherwise, the output of a FF doesn't change until after the clock edge, and the input is only sensitive to changes before the clock edge. \$\endgroup\$ – Dave Tweed Jun 4 '18 at 18:13
  • \$\begingroup\$ I am sorry. I need a more elaborate explanation. Is there a reference I can get? I know that being edge triggered, the FF samples only at the edge, further changes in D won't be carried to Q for the remaining part of the cycle. So if for the first clock edge, the input was 0, it sets, the first Q to zero. On the next clock edge if input was 1, the first Q is set to 1, but the value available at the D of second FF is still 0 (due to Q first being zero) when clock goes high. Is this how a 10 state can be reached? \$\endgroup\$ – supreme_leader Jun 5 '18 at 17:02
  • \$\begingroup\$ Yes, that is correct. \$\endgroup\$ – Dave Tweed Jun 5 '18 at 17:06

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