This is a Verilog model of an array of D flip-flops with enable line along with a test bench used in ModelSim Altera:

module Register_Design #(parameter Width = 4)
    input Clock, Reset, Load, 
    input  [Width - 1:0] In,
    output reg [Width - 1:0] D
    always @(posedge Clock or negedge Reset) begin
            D <= 0;
        else if(Load)
            D <= In;

module Register_Design_Test;
    reg Clock, Reset, Load;
    reg [3:0] In;
    wire [3:0] D;

    Register_Design #(4) REG0 (Clock, Reset, Load, In, D);

    initial fork
        Clock = 1'b0;
        Reset = 1'b1;
        Load  = 1'b1;
        In    = 4'h0;
        #2 Reset = 1'b0;
        #10 In = 4'b0010;
        #20 In = 4'b0100;
        #30 In = 4'b1000;
        #40 In = 4'b1100;
        #40 Load = 1'b1;
        #50 In = 4'b1111;
        #70 In = 4'b1110;
        #80 In = 4'b1100;
        #90 In = 4'b1000;
        #100 In = 4'b0000;

    always @(Clock) #10 Clock <= ~Clock;

    initial #500 $stop;

Here is a picture of the simulation output: enter image description here

As you can see despite the Load input is being 1 which should load a new value into the D flip-flops, the output is always 0000 which is the default state at reset. What am I missing here?

Instead of using a behavioral dataflow model, I used this one and it worked just fine:

D_FF D0 (Clock, Reset, M[0], D[0]);
D_FF D1 (Clock, Reset, M[1], D[1]);
D_FF D2 (Clock, Reset, M[2], D[2]);
D_FF D3 (Clock, Reset, M[3], D[3]);

MUX_2x1 MUX0 ({In[0], D[0]}, Load, M[0]);
MUX_2x1 MUX1 ({In[1], D[1]}, Load, M[1]);
MUX_2x1 MUX2 ({In[2], D[2]}, Load, M[2]);
MUX_2x1 MUX3 ({In[3], D[3]}, Load, M[3]);

module MUX_2x1 (In, S, Out);
    input  S;
    input  [1:0] In;
    output reg Out;

    always @(*) begin
        case (S)
            1'b0:    Out = In[0];
            1'b1:    Out = In[1];
            default: Out = 1'bx;

module D_FF (clk, reset, d, q);
    input d, clk, reset;
    output reg q;

    always @(posedge clk or posedge reset) begin
            q <= 0;
            q <= d;
  • 2
    \$\begingroup\$ Your reset polarity looks to be the wrong way around. You're holding it LOW throughout. \$\endgroup\$ – awjlogan Jun 1 '18 at 15:43
  • 1
    \$\begingroup\$ I hate when this happens :( what a rookie mistake xD \$\endgroup\$ – 3bdalla Jun 1 '18 at 15:48
  • 2
    \$\begingroup\$ Upvote @ThePhoton below, and put it down to experience :) \$\endgroup\$ – awjlogan Jun 1 '18 at 15:49
  • \$\begingroup\$ Already upvoted. But what do I put down? \$\endgroup\$ – 3bdalla Jun 1 '18 at 15:50
  • 2
    \$\begingroup\$ don't worry, it's just a turn of phrase that means you've acknowledged the mistake and won't do it again :) \$\endgroup\$ – awjlogan Jun 1 '18 at 15:51

In your first code sample, you have a low active reset (if (~Reset) D <= 0). And in the testbench you hold Reset low for most of the simulation. As expected this results in D being 0.

In your second code sample you have a high-active reset (if (reset) q <= 0 ) which will naturally behave differently.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.