FPGA how to create delay

Question

I understand that with synchronous FPGA, the whole execution is done in cycles. What happens when my circuit has two parts which give outputs in different cycles (one has greater depth than the other) and I need the outputs in a different part of the circuits in a single cycle? Is there any better way than just adding logic gates which do nothing in order to get delay of the required number of clock cycles?

I know that I usually don't have to care about this when programming FPGA's, but I would like to understand it.

Answer 1

You would use either pipeline registers or FIFOs to take up the delay. Pipeline registers are good for short delays, and you essentially get one cycle of delay per stage. At their simplest, they act like shift registers, but it is also possible to have handshaking between stages. FIFOs are good for longer delays. A FIFO will store the data in an internal RAM for the duration of the delay. Another advantage of a FIFO is that it can cross clock domains.

Answer 2

I’m assuming your FPGA runs on the same clock, so you do not have CDC issues. In that case, have your separate sections output the data in separate buffers.

A processing section can then wait for both buffers to have data available in them. When the data is available you can pop both buffers and do the required processing in the processing section.

This setup also has the advantage that you avoid blocking by the processing section due to the buffering.

Answer 3

If you want to delay results by a certain number of clock cycles, latches/flip flops are a better choice than gates. You can pipe the faster data through the number of stages the slower data needs to catch up. It's essentially a shift register for each bit of the result that needs to be delayed.

Answer 4

If you need to delay a lot of data lines for a lot of clock cycles a delay implementation using RAM blocks might be less resource intensive than just using flipflops. The only things you need here are basically two counters and a dual ported ram and instead of using buswidth * delay-cycles flipflops you are using buswidth * delay-cycles RAM bits plus the overhead of the counters.