enter image description here Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, getting some zigzag signals. Can you share your thoughts on this.

Using Cadence environment, TSMC 180nm Tech

Output Waveforms

Schematic Diagram

  • \$\begingroup\$ Is there RTL associated with this? or, maybe, is this a structural sim... either way is this written in Verilog/VHDL? \$\endgroup\$ – CapnJJ Jun 2 '18 at 1:58
  • \$\begingroup\$ Verilog-A? I am out on this (but, I wish I knew more about Verilog-A) :/ Check/post on Mentor's verficationacademy.com \$\endgroup\$ – CapnJJ Jun 2 '18 at 3:30
  • \$\begingroup\$ All the D-FF's I have seen look rather different. Using two sets of "feed-back inverters" and transmission gates: allthingsvlsi.wordpress.coma/tag/… \$\endgroup\$ – Oldfart Jun 2 '18 at 7:47
  1. @CapnJJ I believe it is custom design with 0.18um.
  2. @Vinay: First of all you need to run realistic simulations. Find ft of your technology. Now find 0.2ft. Set the rise and fall time accordingly for input signals. A realistic input signal is shown in 3 below.
  3. A Non-overlapping two-phase clock generator with adjustable duty cycle
  4. DETFF, The Usage of Dual Edge Triggered Flip-flops in Low Power, Low Voltage Applications
  5. More helpful, Low power dual edge - Triggered static D flip-flop
  6. All the sizes in your schematics are pw, nw and rw. I think you can read up more about analog design before attempting tape out.

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.