I have an 74137 address decoder and know how to build one like that from basic gates. But in my use case the address decoder is connected to the enable pins of a number of bus drivers and I fear this will cause temporary shorts.
So I want to make sure the old bus driver is always disabled before a new bus drivers is enabled. The bus drivers have an active low enable pin so I need an inverting address decoder. Overall the address decoder has to only set the new output to low after setting the old output to high.
How do I build an address decoder like that?
Note: I only need a 2-to-4 address decoder and I can probably extend a 1-to-2 example myself.
(Does any 74xx series chip do this?)
I've created a little test setup with just a 74139 and 2x 74541 and connected the output of the address decoder to an oscilloscope:
What I see is that the 1Y0 and1 Y3 outputs are nearly complements. As Y0 falls Y3 rises at about the same speed. After 15ns they hit the mid point and cross. After 30ns 1Y0 is below 5% and 1Y3 above 95%.
The output of the bus drivers (Y1) only starts to change at 25ns and takes 25ns to reach >95%. So overall it takes 50ns from the time the address inputs change to the bus having switched.
What concerns me is that I see a voltage drop on Vcc from 5V to 4.6V on the switch. Low point is at 15ns, when 1Y0 and 1Y3 are both at 50% level and Vcc comes back to 5V at 30ns when the address decoder has finished switching. Power supply is through USB with a 470uF condensator. All chips also have individual 0.1uF condensators between Vcc and GND.
My conclusion is that I do see the two bus drivers going active at the same time and the resulting short pulls down my limited power supply. And power must not drop below 4.5V as that's the minimum required for other components.
So any tips how best to modify the 74139 or build an address decoder from gates to make it go low only after high on the old output is established? Should I run the outputs through 2 OR gates to delay any falling edge?