I have an 74137 address decoder and know how to build one like that from basic gates. But in my use case the address decoder is connected to the enable pins of a number of bus drivers and I fear this will cause temporary shorts.

So I want to make sure the old bus driver is always disabled before a new bus drivers is enabled. The bus drivers have an active low enable pin so I need an inverting address decoder. Overall the address decoder has to only set the new output to low after setting the old output to high.

How do I build an address decoder like that?

Note: I only need a 2-to-4 address decoder and I can probably extend a 1-to-2 example myself.

(Does any 74xx series chip do this?)


I've created a little test setup with just a 74139 and 2x 74541 and connected the output of the address decoder to an oscilloscope:


simulate this circuit – Schematic created using CircuitLab

What I see is that the 1Y0 and1 Y3 outputs are nearly complements. As Y0 falls Y3 rises at about the same speed. After 15ns they hit the mid point and cross. After 30ns 1Y0 is below 5% and 1Y3 above 95%.

The output of the bus drivers (Y1) only starts to change at 25ns and takes 25ns to reach >95%. So overall it takes 50ns from the time the address inputs change to the bus having switched.

What concerns me is that I see a voltage drop on Vcc from 5V to 4.6V on the switch. Low point is at 15ns, when 1Y0 and 1Y3 are both at 50% level and Vcc comes back to 5V at 30ns when the address decoder has finished switching. Power supply is through USB with a 470uF condensator. All chips also have individual 0.1uF condensators between Vcc and GND.

My conclusion is that I do see the two bus drivers going active at the same time and the resulting short pulls down my limited power supply. And power must not drop below 4.5V as that's the minimum required for other components.

So any tips how best to modify the 74139 or build an address decoder from gates to make it go low only after high on the old output is established? Should I run the outputs through 2 OR gates to delay any falling edge?


simulate this circuit

  • \$\begingroup\$ Your fears seem unfounded. \$\endgroup\$
    – Andy aka
    Commented Jun 2, 2018 at 10:41
  • \$\begingroup\$ What bus drivers do you have, exactly? LS, HC, or something else? \$\endgroup\$ Commented Jun 2, 2018 at 10:46
  • \$\begingroup\$ I am not so sure that this is totally unfounded. A long time ago I spent weeks debugging a subtle corruption issue that caused a memory test error in an embedded system. In the end it was caused by nanosecond level timing difference between OE# pins of SRAM chips and the DIR pin of bidirectional bus buffer. \$\endgroup\$ Commented Jun 2, 2018 at 10:46
  • \$\begingroup\$ The SRAM chips I mentioned were the 2114 type (1Kx4) that were new in the market place at the time of that debugging that I mentioned above. Time frame circa 1980. \$\endgroup\$ Commented Jun 2, 2018 at 10:53
  • \$\begingroup\$ I have 74HCT541, not LS.ls \$\endgroup\$ Commented Jun 2, 2018 at 10:58

2 Answers 2


First, note that typical systems have separate chip-selects vs. read and write strobes. These are separated in time to avoid exactly this issue, with dead times inserted to allow for select and bus switching. In other words, real systems don’t have this problem because they separate address/chip select from data timing.

In your case, you’re looking at the wrong problem. It is expected that there will be an address + chip select instability time, where two devices might be selected at the same time while the address and decoding propagates. What you need then is a sequencer that delays asserting an OE or WE to allow for this settling time. Then you won’t have clashes.

  • \$\begingroup\$ That "sequencer that delays asserting an OE" bit is what I'm asking for. How do you build that? \$\endgroup\$ Commented Aug 27, 2021 at 18:20
  • \$\begingroup\$ As part of your clock generation, you’d use a faster clock (say, 8x) to separate each machine cycle into phases. You’d use a small finite state machine to generate the gating signals. \$\endgroup\$ Commented Aug 27, 2021 at 19:58

Your 74HCT541 has an output transition time of 5 nanoseconds, typical, when driving a capacitive load. While switching, the capacitive load behaves like a short.

That means the 74HCT541 is okay with getting its outputs shorted for 5ns. The overlap between two outputs of your decoder being enabled will be on the order of 2ns, if it happens at all.

Just connect it without any circuitry to avoid short overlaps like this, it'll be fine.

EDIT: If you use a 74LS137 instead of a 74HCT137, the chip will actually pull its outputs high before pulling another one low. You can see that from tPLH being smaller than tPHL. So just select a decoder where that's the case.

  • \$\begingroup\$ Even if that happens every 50ns? What did they do in the 74LS137 to make it low after high? \$\endgroup\$ Commented Jun 2, 2018 at 11:17
  • \$\begingroup\$ @GoswinvonBrederlow Yes, it should be fine even then. LS (and other bipolar TTL) parts are built from NPN transistors with pull-ups (plus a totem-pole output stage) which simply transitions faster from high to low than from low to high. It depends on the chip, though, so you should look at tPLH and tPHL. CMOS parts, like HC, usually have symmetric propagation delays (tPLH = tPHL) \$\endgroup\$ Commented Jun 3, 2018 at 23:38
  • \$\begingroup\$ The difference between tPLH and tPHL just means one transition takes longer. But both start at the same time and overlap. That is a far cry from "low after high". \$\endgroup\$ Commented Jun 5, 2018 at 7:54

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