Designing an Over-Current Protection Circuit with Delayed Reset

Question

As part of a larger design I am trying to monitor current through a wire and cut it off if it exceeds a threshold. After the current has been turned off it should remain off for a minimum time period and only turn back on when a reset button is pressed.

The circuit below is my current design idea. I'm looking for any reason why this wouldn't work, as well as hearing any suggestions for better designs (excluding software solutions).

• The current sensor will output a voltage proportionate to the current through the wire, causing the op-amp to output a high signal when it exceeds a REF voltage.
• This will trigger the monostable circuit to produce a high signal for a set period, setting the data pin low and turning on the Latch Enable (LE) to read in that low.
• The high-pulse also switches the Output Enable (OE) pin on the D-latch, the Output goes to high-impedance and the NFET is turned off by R3. (Possibly unnecessary but it doesn't hurt)
• Once the pulse has finished the LE pin is driven low and the data pin is high. I think I might have to introduce some small delay for the data pin here so that the D-Latch doesn't read in the high-going data pin but instead keeps its value latched at low?
• The OE pin is released again and the D-latch should output its latched-to state of low. Once the button is pressed the data pin is read again and the output switched on, allowing current to flow.

^{simulate this circuit – Schematic created using CircuitLab}

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EDITS:

Added R5, C1 to provide a delay of 2ms at data pin. This is the time to charge from 0 to 2V (minimum V_IH @ 3.3V supply) with 3.3V applied. Data pin must be stable for only a few ns after LE goes low so this should be plenty of headroom

Added R6, R7 to provide 25mV of hysteresis for the op-amp which corresponds to a change of 100mA through the load

Answer 1

Maybe you can join the current sensor , latch and comparator in one like in the below schematic.

OA1 use only positive hysteresis through D1 diode, this simplifies the design since the threshold voltage is Vref without any added hysteresis.

When OA1 is triggered (outputs high) and voltage on Rsense (R3) is zero R2 , R5 and R1 must give an OA1 V+ voltage higher than maximum Vref so as no matter the voltage on R3 OA1 will stay high.

SW1 (reset switch) removes the positive feedback allowing OA1 output to go low.

On pressing SW1 R1 and R5 divide the current sensing voltage on R3 allowing a small startup overload

M1 is opened when both OA1 and the monostable outputs low

Of course, you have to put a proper MOSFET driver on the NOR output.

^{simulate this circuit – Schematic created using CircuitLab}

A version without a monostable can be figured with a schmitt trigger gate but you will have to wait the specified time after pressing the reset for M1 to open.

Update for an example of R1, R2, R5 values

Max current to trigger the protection Imax = Vref/R3, here is 500mV/0.050 ohm = 10A

Power dissipated on R3 at max current Pr3= Vref*Vref/R3 = 5W

We pick for R1 a value higher enough to not endanger OA1 input in case of R3 failure and lower enough to be less sensitive to noise. If 3mA is acceptable for the OA input protection diode then 30V/0.003A = 10kohm value will do.

R5 value depends on the acceptable overcurrent percentage while pressing the switch. If we want 200% then (R1+R5)/R5 = 2 , R5 = 10kohm

R2 is there only to protect OA1 output and it's maximum value is limited by the condition that OA+ voltage when the output is high to be higher than Vref at any time even with R3 voltage zero and maximum Vref to keep OA high state locked until the switch is pressed.

That leads to condition (Vo-Vd1)*R1/(R2+R5+R1)>Vref where Vo and Vd1 are the max output voltage of OA1 and D1 voltage.

For Vo - Vd1 = 3V , R2 can be any value less than 40kohm but also acceptable as load for OA1 output , we can pick also 10kohm for that to.

I have an update since the answer is somehow incomplete without the monostable implementation. On this website I found one using two NOR gates which gives you the opportunity to use a single quadruple NOR 74LS02 for the existent NOR gate to.

The second issue could be with the current sense resistor of 0.05ohm 5W. The 5W power is at the maximum current but if you find that is to inefficient you can use a current/voltage transducer as you said.

The issue with current transducers is that a DC transducer is hard to find and deprecated most of them are AC transducers that outputs a Vcc/2 centered voltage.

If you find a DC transducer you can connect the output to R1 and keep everything else as is only scaling Vref accordingly.

For an AC transducer you need to subtract the Vcc/2 so use the following schematic:

^{simulate this circuit}

Answer 2

While this would would work, a simpler solution would be a basic RC circuit connected to a CMOS inverter which is fed from your op-amp output; When the OP-Amp sends the signal, the RC circuit charges to the max voltage, effectively shutting off the CMOS inverter, and after the transient dies down, based on your specified time constant, the CMOS inverter is back, Voila!!!