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I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C). Can anyone confirm or correct me ?

PS: The steps I made are attached

MOS layout

enter image description here

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  • \$\begingroup\$ I can do it (made my own logic cell library recently) but I'm too lazy. You should show the steps you have taken like draw NMOS/PMOS over the layout then re-arrange the schematic. Then perhaps someone will check. \$\endgroup\$ – Bimpelrekkie Jun 3 '18 at 10:26
  • \$\begingroup\$ I have included the steps taken. Thanks for your note \$\endgroup\$ – CE952015 Jun 3 '18 at 10:35
  • \$\begingroup\$ I agree up to the truth table. I disagree with AND(not(AB),C) as that would mean Ouput can only be one when C = 1 but that is not so in the table. \$\endgroup\$ – Bimpelrekkie Jun 3 '18 at 10:44
  • \$\begingroup\$ I guess it should be Not(C) instead of C, which makes it NOT(AB+C) \$\endgroup\$ – CE952015 Jun 3 '18 at 10:54
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Your truth table for the circuit is correct, but your logic expression does not describe the table.

Try writing out the truth table for the expression and comparing it to the one for the circuit.

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  • \$\begingroup\$ I guess it should be Not(C) instead of C \$\endgroup\$ – CE952015 Jun 3 '18 at 10:54
  • \$\begingroup\$ Yes. And using DeMorgan's, AND(NOT (AB), NOT(C)) reduces to NOT(OR (AB), (C)). Keep in mind that any single CMOS logic circuit always involves a NOT wrapped around positive logic. You can read the logic pretty much directly by looking at the series/parallel connections in the NMOS network only. \$\endgroup\$ – Dave Tweed Jun 3 '18 at 11:08
  • \$\begingroup\$ Yes, thank you very much. Basic deMorgan and logic expressions optimizing is not my actual problem here. I am really unsure about the layout itself, and if the schematic is correct. About your comment "You can read the logic pretty much directly by looking at the series/parallel connections in the NMOS network only", why is that true? we never take into consideration the pMos part connected to the Vdd? \$\endgroup\$ – CE952015 Jun 3 '18 at 11:18
  • \$\begingroup\$ You just need to make sure that the PMOS network is the logical complement of the NMOS network -- parallel connections exchanged for series connections. But it contains no additional information about the logic function. \$\endgroup\$ – Dave Tweed Jun 3 '18 at 11:31

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