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I have read a paper about the cold-boot attack led by J. Alex Halderman. Full pdf: https://jhalderm.com/pub/papers/coldboot-sec08.pdf

The paper shows the decay of a data in memory without power. They used this picture as example: enter image description here

Obviously, the discharged state for some capacitors are represented as 1(white) others as 0(black).

What is the reason for this? Why not represent every discharged capacitor as 0? Can you give me some insight in this topic, or keywords I can further research?

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This is addressed in the paper, in the second paragraph of section 3:

Over time, charge will leak out of the capacitor, and the cell will lose its state or, more precisely, it will decay to its ground state, either zero or one depending on whether the fixed conductor of the capacitor is hard-wired to ground or power.

As charge leaks from the capacitor, the voltage difference across its terminals goes to zero, and the "ground state" of what you can read afterwards is just the voltage on the other end of the capacitor.

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    \$\begingroup\$ This doesn't really help me, it just changes the question to something like why are some capacitors hard-wired to ground and some to power? why not all to ground? \$\endgroup\$
    – pipe
    Commented Jun 3, 2018 at 22:55
  • \$\begingroup\$ After a bit of digging through the references and searching around in other places, I still couldn't really find a good answer to why some capacitors are connected to ground and others to power. Wikipedia mentions briefly that most modern DRAM has the capacitor connected to Vcc/2 for faster performance, but the source for that is incomplete. I haven't been able to find anything relevant with further searching, either. I'm pretty stumped myself, too. If I had to hazard a guess, I'd say that it's probably some physical limitation of the fabrication process -- but that's really just a guess. \$\endgroup\$
    – Persona
    Commented Jun 4, 2018 at 4:20
  • \$\begingroup\$ @pipe if you have institutional access, this paper (referenced from the other) suggests the reason why. From what I can understand from the short description in that paper is that all capacitors are connected to Vcc/2 on the fixed side, and they store +Vcc/2 for a one, and -Vcc/2 for a zero (bipolar sense amp). For symmetry reasons, half the cells end up wired in an inverse polarity where -Vcc/2 is a one and +Vcc/2 is a zero. \$\endgroup\$
    – Tom Carpenter
    Commented Jun 4, 2018 at 7:41
  • \$\begingroup\$ Figure 1 of this paper as seen here indicates that the fixed conductor of every capacitor is hard wired to power, but instead some bitlines are inverted. Are this different architectures that try to solve the same problem? \$\endgroup\$
    – dead_values
    Commented Jun 5, 2018 at 9:45

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