I am working on audio preamplifier project using Altium Designer, which is also a great opportunity to learn this particular piece of software. Now, I've selected Hierarchical design to be able to get benefits of Multi-Sheet and Multi-Channel Design:

Project Options

Now, I have 8 audio relays, implemented with Repeat(AUDIO_INPUT_RELAY,1,8) command:

Audio Input Relays

and here is Audio Input Relay Schematic itself:

Audio Input Relay Schematic

Now, these 8 audio input relays converge into single SELECTED_AUDIO_OUTPUT_LEFT and single SELECTED_AUDIO_OUTPUT_RIGHT lines and here is whole subsheet:

Audio Inputs Relays System

I am aware a volume control is missing (the project is not finished), however, this is not topic now and my question is: when I compile this project, why do I get following error (I am aware I can disable error reporting in Project Options, which is also not the point here, I want to know what did I wrong):


and screenshot of error:

Compile Error I have no unmatched ports and sheet entries, as @Radiohead gave a hint: Sync ports to sheet entries


2 Answers 2


I think the problem might be that those ports, since they do not share a common name, Altium is unable to bind them together (even though you did so by using a wire).

This should fix it:

Design -> Synchronize Sheet Entries and Ports

There you'll have a menu with the available ports and sheet entries and you can assign them to each other, compile and everything should be fine.


So, I've tried on Altium 16 to do a project more or less like yours.

First, I tried with two joined modules, with different entry and exit port names. enter image description here

And I get a few warning because of that, but the project compiles enter image description here

Then, when I assign the same name to entry and exit ports it compiles successfully (no warnings) enter image description here

Try assigning the same name to the ports and compile again, see if it helps

  • \$\begingroup\$ Hmm, it just got weirder: I've put same names on exit and entry ports, same error ports. However, when I've set the direction of exit ports (MODULE1.SchDoc in your project) to Bidirectionalinstead of Output (which they actualy are in my project), the error got away. Why? \$\endgroup\$ Jun 4, 2018 at 11:19
  • 1
    \$\begingroup\$ Bidirectional works, because it lets each port to assert the state of the line. e.g. CAN Bus, where there is multimaster. ' \$\endgroup\$ Jun 4, 2018 at 12:42

For Altium, an Output Port asserts a signal the net. Logically, a net cannot be asserted different values by different sources,which makes it undefined. Altium cannot guess impedances of the ports,so unlesa you know what you do, it will assume this logical error.

I would get another sheet that "adds" the signals up and outputs the "sum"

I am writing this from the app, couldn't check you schematics honestly. Will do in 5 mins.

All right. This is not different from connecting output of 8 different ports to the same net, and then to an input port. I think the root cause is the fact that you are effectively connecting 8 different ports to one port. Altium doesn't know, of course whether this is sensible or not. We generally don't "add signals up" without an impedance or a resistance is in place.

You can do several things. One is to put a NoERC directive on the Net, it you are absolutely sure that the way that is interpreted right.

You can create a sheet that has 8 input ports that execute the adding functionality.


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