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I'm trying to work out worst-case propagation delays for an address-decode circuit I'm designing. I'm looking at the datasheet for a 74HC00N, and I'm confused by the propagation delay (tpd) values on p6 of the datasheet:

enter image description here

Focusing on the Vcc=4.5 V section, there are three lines:

  • TA=25˚C
  • SN54HC00
  • SN74HC00

I understand that the first line is indicating values where the ambient temperature is 25˚C, and the the next two lines are values for the two IC versions covered by the datasheet (54xx and 74xx). But one of these things is not like the other. If I'm using the SN74HC00, the datasheet says that the max tpd is 23ns. So when does the 18ns tpd value apply? The only explanation I could think of is that at TA=25˚C, both the 54xx and the 74xx versions exhibit the 18ns max, but above 25˚C, the max values diverge to the other values listed. Is that the correct interpretation?

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  • \$\begingroup\$ That is correct. \$\endgroup\$
    – Andy aka
    Jun 5 '18 at 11:37
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    \$\begingroup\$ Note that instead of using discrete logic, depending on the space/power/cost constraints, a faster/more flexible solution could be to use programmable logic. \$\endgroup\$
    – crj11
    Jun 5 '18 at 14:06
  • \$\begingroup\$ @crj11 that's a great point. This is a personal learning project to design and build an 8-bit computer, so I was limiting myself to 65cxx chips and 74xx logic chips as a design constraint. But PLDs have been around since the late 60s. The C-64 used a PAL for all sorts of device address decode logic. I am using only new (currently produced) parts; perhaps if I stick to thru-hole components it will still be in the spirit of the thing. \$\endgroup\$ Jun 6 '18 at 1:57
  • \$\begingroup\$ @JasonClark If you want to use vintage parts, the 16V8 type parts would be a good start. The big problem there is that the older PLDs require a separate programmer to program them before mounting them on the board. Modern parts can be programmed in circuit via a JTAG interface. As long as you have the space and the prop delays are not an issue, the discrete logic is probably easier to deal with. Of course if you get a really big CPLD or a small FPGA, you could put the whole CPU inside it like hackaday.com/2014/08/16/an-fpga-based-6502-computer . \$\endgroup\$
    – crj11
    Jun 6 '18 at 2:35
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The 54xx series of logic is just the same chip specified for a larger temperature range, so it has a higher worst case propagation delay at the temperature extremes.

The 54xx chips are characterized over a larger temperature range and usually tested a bit more comprehensively so that they are suitable for military applications.

Since they are the same chip, the worst case delay for the 54xx and 74xx series is the same at 25C.

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The actual silicon in both 54HC00 and 74HC00 is the same. That's why they both have a maximum time of 18nS at 25C.

The 74HC00 (commercial grade) is only rated over the temperature range of -40 to +85, whereas the 54HC00 (military grade) covers -55 to +125. The 54 version will be slower over its temperature range.

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