In LTSpice, I'd like to 'soften' the 'knee' of the transition between triode and saturation curves. For a JFET, lowering Vto achieves this - but also affects the ratios of the VGS 'branch' voltages when plotting Id vs VDS.
It is possible to adjust Vto and B such that the saturation curves match measured characteristics, and various ways to get an initial estimate for Vto, Beta, Lamda and Rs from the curves exist.
Having done so, is there another significant parameter which allows 'knee softening' without affecting the ratios of the VGS 'branch' voltages?
The question here concerns modeling JFET & MOSFET devices.
However, I wonder if I am seeing a limitation of the modeling? I note that for "VDMOS" (not what I'm modeling) this link mentions - "...independent fits to the saturation and linear regions of the output characteristics."