# SPICE model DC Sweep, triode region, factors other than Vto affecting knee slope (JFET or MOSFET)

In LTSpice, I'd like to 'soften' the 'knee' of the transition between triode and saturation curves. For a JFET, lowering Vto achieves this - but also affects the ratios of the VGS 'branch' voltages when plotting Id vs VDS.

It is possible to adjust Vto and B such that the saturation curves match measured characteristics, and various ways to get an initial estimate for Vto, Beta, Lamda and Rs from the curves exist.

Having done so, is there another significant parameter which allows 'knee softening' without affecting the ratios of the VGS 'branch' voltages?

The question here concerns modeling JFET & MOSFET devices.

However, I wonder if I am seeing a limitation of the modeling? I note that for "VDMOS" (not what I'm modeling) this link mentions - "...independent fits to the saturation and linear regions of the output characteristics."

• Put a resistor in parallel? Put a resistor in series? Maybe you can draw a picture of what you don't want then superimpose what you do want. – Andy aka Jun 5 '18 at 14:23
• Hi - I'm ideally wanting to use only the SPICE parameters. – SJB Jun 5 '18 at 14:56
• Try playing around with lambda and Ksubthres (for VDMOS), though, I warn you, you might not get quite what you expect. I leave it to you to find out, maybe, indeed, it's what you're after. – a concerned citizen Jun 5 '18 at 16:36
• Is it fair to say then. The JFET/MOSFET modelling is "lacking" the Ksubthres parameter? – SJB Jun 5 '18 at 17:20
• Related question - Does Rds = Rd + Rs? – SJB Jun 5 '18 at 17:22